gem5/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 113478                       # Simulator instruction rate (inst/s)
host_mem_usage                                 159608                       # Number of bytes of host memory used
host_seconds                                     0.05                       # Real time elapsed on the host
host_tick_rate                                 165749                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        5642                       # Number of instructions simulated
sim_seconds                                  0.000000                       # Number of seconds simulated
sim_ticks                                        8312                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses                981                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency            3                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency            2                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                    891                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency            270                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.091743                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   90                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency          180                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.091743                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              90                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               821                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency     2.737500                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency            2                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   741                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency           219                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.097442                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                  80                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency          146                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.088916                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             73                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   9.600000                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                1802                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency     2.876471                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency            2                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    1632                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency             489                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.094340                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   170                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency          326                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.090455                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              163                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses               1802                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency     2.876471                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   1632                       # number of overall hits
system.cpu.dcache.overall_miss_latency            489                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.094340                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  170                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency          326                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.090455                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             163                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    170                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                112.055094                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     1632                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.icache.ReadReq_accesses               5643                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency     2.996390                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency     1.996390                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                   5366                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency            830                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.049087                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  277                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency          553                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.049087                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             277                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  19.371841                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                5643                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency     2.996390                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency     1.996390                       # average overall mshr miss latency
system.cpu.icache.demand_hits                    5366                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency             830                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.049087                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   277                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency          553                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.049087                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              277                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses               5643                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency     2.996390                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency     1.996390                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                   5366                       # number of overall hits
system.cpu.icache.overall_miss_latency            830                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.049087                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  277                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency          553                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.049087                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             277                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.sampled_refs                    277                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                133.267292                       # Cycle average of tags in use
system.cpu.icache.total_refs                     5366                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses               447                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency     1.968610                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency            1                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency           878                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.997763                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 446                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency          439                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.982103                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            439                       # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.002242                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                447                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency     1.968610                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency            878                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.997763                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  446                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency          439                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.982103                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             439                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses               447                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency     1.968610                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     1                       # number of overall hits
system.cpu.l2cache.overall_miss_latency           878                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.997763                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 446                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency          439                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.982103                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            439                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   446                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               245.259112                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                                0                       # number of cpu cycles simulated
system.cpu.num_insts                             5642                       # Number of instructions executed
system.cpu.num_refs                              1792                       # Number of memory references
system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls

---------- End Simulation Statistics   ----------