2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 0.177135 # Number of seconds simulated
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sim_ticks 177134936000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 142557 # Simulator instruction rate (inst/s)
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host_tick_rate 41921641 # Simulator tick rate (ticks/s)
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host_mem_usage 216920 # Number of bytes of host memory used
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host_seconds 4225.38 # Real time elapsed on the host
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sim_insts 602359810 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 48 # Number of system calls
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2011-09-13 18:58:09 +02:00
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system.cpu.numCycles 354269873 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 91159436 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 84245505 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 4004866 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 86334569 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 80046410 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.usedRAS 1704802 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 1819 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 76808344 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 703901675 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 91159436 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 81751212 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 159188980 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 18469359 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 103024732 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 658 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 74435954 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1343690 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 353410599 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.128136 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.980644 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 194221784 54.96% 54.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 25626631 7.25% 62.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 19263980 5.45% 67.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 24389254 6.90% 74.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 11789340 3.34% 77.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 13441910 3.80% 81.70% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 4603453 1.30% 83.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 7798173 2.21% 85.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 52276074 14.79% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 353410599 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.257316 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.986908 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 98916904 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 83485006 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 137131028 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 19492362 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 14385299 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 6301332 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 2598 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 740264204 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 7138 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 14385299 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 111881934 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 9577242 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 106466 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 143552765 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 73906893 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 727334722 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 296 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 59781135 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 10308783 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 341 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 753003460 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 3381092272 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 3381092144 # Number of integer rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 125586053 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 6434 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 6436 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 132024310 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 179771780 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 82868403 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 19149565 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 24496609 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 702530034 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 7346 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 663102893 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 740706 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 99626728 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 237214631 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 1047 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 353410599 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.876296 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.734600 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 85472706 24.19% 24.19% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 90623075 25.64% 49.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 75986397 21.50% 71.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 42524156 12.03% 83.36% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 25503318 7.22% 90.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 18123112 5.13% 95.71% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 7244001 2.05% 97.76% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 6628954 1.88% 99.63% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1304880 0.37% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 353410599 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::IntAlu 202122 4.87% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 2984901 71.87% 76.73% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 966402 23.27% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 412611240 62.22% 62.22% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 6564 0.00% 62.23% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 172508534 26.02% 88.24% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 77976552 11.76% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 663102893 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.871745 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 4153425 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.006264 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 1684510480 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 802175669 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 650244511 # Number of integer instruction queue wakeup accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 667256298 # Number of integer alu accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 29664426 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 30819183 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 223952 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 11801 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 12647388 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 13674 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 12619 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 14385299 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 811787 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 58163 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 702606824 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 1856146 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 179771780 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 82868403 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 6016 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 13064 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 5095 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 11801 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4163103 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 495424 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 4658527 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 656117429 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 169139334 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 6985464 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_nop 69444 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 245837823 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 76466943 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 76698489 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.852027 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 652257551 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 650244527 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 423314128 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 657393243 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.835450 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.643928 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 100255909 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 6299 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 4064207 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 339025301 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.776740 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.152545 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 108189269 31.91% 31.91% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 106528342 31.42% 63.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 49314404 14.55% 77.88% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 9858111 2.91% 80.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 23334525 6.88% 87.67% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 14310366 4.22% 91.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 7925881 2.34% 94.23% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 1332062 0.39% 94.62% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 18232341 5.38% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 339025301 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 602359861 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.refs 219173611 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 148952596 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 1328 # Number of memory barriers committed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.branches 70828603 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.int_insts 533522647 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 997573 # Number of function calls committed.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 18232341 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 1023408118 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 1419658807 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 37049 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 859274 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 602359810 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.588137 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.588137 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.700285 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.700285 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3276148182 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 676030301 # number of integer regfile writes
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 943785902 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 2660 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 38 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 657.730766 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 74434959 # Total number of references to valid blocks.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.avg_refs 97812.035480 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 657.730766 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.321158 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 74434959 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 74434959 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 74434959 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 995 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 995 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 995 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 34724500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 34724500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 34724500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 74435954 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 74435954 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 74435954 # number of overall (read+write) accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34898.994975 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34898.994975 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34898.994975 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 234 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 234 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 234 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 761 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 761 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 25975000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 25975000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 25975000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34132.720105 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 441231 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4094.754255 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 205797010 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 445327 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 462.125607 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 87838000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4094.754255 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999696 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 137942409 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 67851936 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 1336 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 205794345 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 205794345 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 249307 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1565595 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses 8 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 1814902 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1814902 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 3284045500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 27041000027 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 163000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 30325045527 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 30325045527 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 138191716 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 207609247 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 207609247 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.001804 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.022553 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.005952 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.008742 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.008742 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 13172.696715 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 17272.027585 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 20375 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 16708.916254 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 16708.916254 # average overall miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 395260 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 51378 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1318197 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 8 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1369575 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1369575 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 197929 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 247398 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 445327 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 445327 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1625138000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2544850527 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4169988527 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4169988527 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8210.711922 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10286.463621 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.replacements 72978 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 17806.299437 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 422221 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 88511 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 4.770266 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 1880.880475 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 15925.418963 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.057400 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.486005 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 165873 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 395260 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 189038 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 354911 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 354911 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 32814 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 91177 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1126440500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2003739500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 3130180000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 3130180000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 198687 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 395260 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 247401 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 446088 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 446088 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.165154 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.235904 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.204392 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.204392 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34328.045956 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34332.359543 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34330.807111 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34330.807111 # average overall miss latency
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 58123 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 8 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32806 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 91169 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1019567500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822366000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2841933500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2841933500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165114 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235904 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.204374 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.204374 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31078.689874 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31224.680020 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
