2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.181028 # Number of seconds simulated
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sim_ticks 181028108500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 110603 # Simulator instruction rate (inst/s)
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host_tick_rate 33239774 # Simulator tick rate (ticks/s)
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host_mem_usage 263548 # Number of bytes of host memory used
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host_seconds 5446.13 # Real time elapsed on the host
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sim_insts 602359805 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 48 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 362056218 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 93448154 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 85911629 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3923569 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 88397798 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 81789381 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.usedRAS 1790445 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 1821 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 79878814 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 718366767 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 93448154 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 83579826 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 162526152 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 20714981 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 102669649 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 77174070 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1530906 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 361172763 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.127936 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.978152 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 198646777 55.00% 55.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 25571456 7.08% 62.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 19827264 5.49% 67.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 25093348 6.95% 74.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 12488036 3.46% 77.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 13650153 3.78% 81.76% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 4767489 1.32% 83.08% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 7787203 2.16% 85.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 53341037 14.77% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 361172763 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.258104 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.984130 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 102343616 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 83020024 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 140521738 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 19192459 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 16094926 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 6886310 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 2563 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 756045465 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 7091 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 16094926 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 115645953 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 9675212 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 105916 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 146342748 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 73308008 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 741744489 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 59347402 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 10155907 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 308 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 765934734 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 3449682594 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 3449682466 # Number of integer rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
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2011-08-19 22:08:08 +02:00
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system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 138517335 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 6417 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 6420 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 130475053 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 183427028 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 85118109 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 19617047 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 24959505 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 714042486 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 7344 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 668482439 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 813187 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 110903932 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 272103092 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 1046 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 361172763 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.850866 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.720469 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 89609578 24.81% 24.81% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 92103808 25.50% 50.31% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 76957239 21.31% 71.62% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 43677932 12.09% 83.71% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 26190048 7.25% 90.96% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 17902760 4.96% 95.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 7158113 1.98% 97.90% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 6378593 1.77% 99.67% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1194692 0.33% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 361172763 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 174743 4.36% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.36% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 2924154 73.03% 77.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 905037 22.60% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::IntAlu 414572332 62.02% 62.02% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 6557 0.00% 62.02% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 174888345 26.16% 88.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 79015202 11.82% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 668482439 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.846350 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 4003934 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.005990 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 1702954726 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 825626408 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 654174988 # Number of integer instruction queue wakeup accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 672486353 # Number of integer alu accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 28890587 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 34474432 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 123741 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 677004 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 14897095 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 16171 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 12604 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 16094926 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 778321 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 50892 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 714119394 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2033981 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 183427028 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 85118109 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 6015 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 12993 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 677004 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4081658 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 498372 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 4580030 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 660769173 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 171345747 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 7713266 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_nop 69564 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 248875630 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 76892303 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 77529883 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.825046 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 656292597 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 654175004 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 424501609 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 659455960 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 1.806833 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.643715 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 111769419 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 6298 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 3982936 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 345077838 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.745577 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.124891 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 111837000 32.41% 32.41% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 108539519 31.45% 63.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 49573446 14.37% 78.23% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 10197254 2.96% 81.18% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 23493632 6.81% 87.99% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 14599312 4.23% 92.22% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 8154465 2.36% 94.59% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 1281875 0.37% 94.96% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 17401335 5.04% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 345077838 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 602359856 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.refs 219173609 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 148952595 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 1328 # Number of memory barriers committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branches 70828602 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.int_insts 533522643 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 997573 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 17401335 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 1041805166 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 1444392656 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 37065 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 883455 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 602359805 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.601063 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.601063 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.663719 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.663719 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3299876653 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 679084326 # number of integer regfile writes
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.misc_regfile_reads 960654614 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 2658 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 39 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 659.213464 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 77173072 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 101410.081472 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 659.213464 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.321882 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 77173072 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 77173072 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 77173072 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 998 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 998 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 998 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 34962500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 34962500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 34962500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 77174070 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 77174070 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 77174070 # number of overall (read+write) accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35032.565130 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35032.565130 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35032.565130 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 762 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 762 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 762 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 26035000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 26035000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 26035000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34166.666667 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 441073 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4094.780664 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 208769486 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 445169 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 468.966810 # Average number of references to valid blocks.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 4094.780664 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999702 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 140903051 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 67863771 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 1333 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 208766822 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 208766822 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 249137 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1553760 # number of WriteReq misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_misses 1802897 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1802897 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 3284237500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 27026235527 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 199500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 30310473027 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 30310473027 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 141152188 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 1342 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 210569719 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 210569719 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.001765 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.022383 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.006706 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.008562 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.008562 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 13182.455838 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 17394.086298 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 22166.666667 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 16812.093551 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 16812.093551 # average overall miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 395116 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 51340 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1306387 # number of WriteReq MSHR hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 1357727 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1357727 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 197797 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 247373 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 445170 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 445170 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1624472000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2544428527 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4168900527 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4168900527 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8212.824259 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.797266 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.replacements 72968 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 17823.256167 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 421257 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 4.760396 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 1903.843188 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 15919.412978 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.058101 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.485822 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 165755 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 395116 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 189016 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 354771 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 354771 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 32799 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 58360 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 91159 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 91159 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1126738500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2004231000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 3130969500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 3130969500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 198554 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 395116 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 247376 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 445930 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 445930 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.165189 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.235916 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.204424 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.204424 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34352.830879 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34342.546265 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34346.246668 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34346.246668 # average overall miss latency
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.writebacks 58122 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32790 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 58360 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020255000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822537500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2842792500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2842792500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165144 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235916 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.204404 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.204404 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.821592 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31229.223783 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
