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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_seconds 51.323721 # Number of seconds simulated
sim_ticks 51323721423000 # Number of ticks simulated
final_tick 51323721423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
host_inst_rate 88242 # Simulator instruction rate (inst/s)
host_op_rate 103686 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5307363437 # Simulator tick rate (ticks/s)
host_mem_usage 679356 # Number of bytes of host memory used
host_seconds 9670.29 # Real time elapsed on the host
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_insts 853325819 # Number of instructions simulated
sim_ops 1002674190 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu.dtb.walker 203200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 189632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5727200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 73778504 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory
system.physmem.bytes_read::total 80318312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5727200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5727200 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 68723904 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_written::total 68744484 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 3175 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2963 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 105440 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1152802 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1270939 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1073811 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_writes::total 1076384 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 3959 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 3695 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 111590 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1437513 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8179 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1564935 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 111590 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 111590 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1339028 # Write bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_write::total 1339429 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1339028 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 3959 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 3695 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 111590 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1437914 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2904365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1270939 # Number of read requests accepted
system.physmem.writeReqs 1076384 # Number of write requests accepted
system.physmem.readBursts 1270939 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1076384 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 81299584 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 40512 # Total number of bytes read from write queue
system.physmem.bytesWritten 68742976 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 80318312 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 68744484 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 633 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 142017 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 76590 # Per bank write bursts
system.physmem.perBankRdBursts::1 80112 # Per bank write bursts
system.physmem.perBankRdBursts::2 82312 # Per bank write bursts
system.physmem.perBankRdBursts::3 76894 # Per bank write bursts
system.physmem.perBankRdBursts::4 75148 # Per bank write bursts
system.physmem.perBankRdBursts::5 84486 # Per bank write bursts
system.physmem.perBankRdBursts::6 75307 # Per bank write bursts
system.physmem.perBankRdBursts::7 76047 # Per bank write bursts
system.physmem.perBankRdBursts::8 76921 # Per bank write bursts
system.physmem.perBankRdBursts::9 104197 # Per bank write bursts
system.physmem.perBankRdBursts::10 75653 # Per bank write bursts
system.physmem.perBankRdBursts::11 81028 # Per bank write bursts
system.physmem.perBankRdBursts::12 74845 # Per bank write bursts
system.physmem.perBankRdBursts::13 77383 # Per bank write bursts
system.physmem.perBankRdBursts::14 76622 # Per bank write bursts
system.physmem.perBankRdBursts::15 76761 # Per bank write bursts
system.physmem.perBankWrBursts::0 64108 # Per bank write bursts
system.physmem.perBankWrBursts::1 67910 # Per bank write bursts
system.physmem.perBankWrBursts::2 69982 # Per bank write bursts
system.physmem.perBankWrBursts::3 67432 # Per bank write bursts
system.physmem.perBankWrBursts::4 65959 # Per bank write bursts
system.physmem.perBankWrBursts::5 70786 # Per bank write bursts
system.physmem.perBankWrBursts::6 64733 # Per bank write bursts
system.physmem.perBankWrBursts::7 66187 # Per bank write bursts
system.physmem.perBankWrBursts::8 67287 # Per bank write bursts
system.physmem.perBankWrBursts::9 71812 # Per bank write bursts
system.physmem.perBankWrBursts::10 65064 # Per bank write bursts
system.physmem.perBankWrBursts::11 69201 # Per bank write bursts
system.physmem.perBankWrBursts::12 65082 # Per bank write bursts
system.physmem.perBankWrBursts::13 66370 # Per bank write bursts
system.physmem.perBankWrBursts::14 66024 # Per bank write bursts
system.physmem.perBankWrBursts::15 66172 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
system.physmem.totGap 51323720227500 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readPktSize::6 1249654 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.writePktSize::6 1073811 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 646219 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 339232 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 151287 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 128129 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 684 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 489 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 533 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 812 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 936 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 166 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::15 11927 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 14439 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 31518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44897 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 53343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 63481 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 63532 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 67021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 67803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 70464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 69167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 70329 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 66867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 85010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 86471 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 65847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 69713 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 62929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1006 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 572 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 637 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 503 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 415 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 414 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 481355 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 311.708207 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 178.914901 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 339.146013 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 186832 38.81% 38.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 113175 23.51% 62.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 45398 9.43% 71.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 23450 4.87% 76.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 18101 3.76% 80.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11671 2.42% 82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10460 2.17% 84.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8315 1.73% 86.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 63953 13.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 481355 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61522 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.647411 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 265.936082 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 61519 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 61522 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61522 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.458942 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.948779 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 6.823778 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 58490 95.07% 95.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 664 1.08% 96.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 448 0.73% 96.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 190 0.31% 97.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 308 0.50% 97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 527 0.86% 98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 143 0.23% 98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 33 0.05% 98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 36 0.06% 98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 18 0.03% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 32 0.05% 98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 22 0.04% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 426 0.69% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 45 0.07% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 33 0.05% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 35 0.06% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 13 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 31 0.05% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61522 # Writes before turning the bus around for reads
system.physmem.totQLat 31530968444 # Total ticks spent queuing
system.physmem.totMemAccLat 55349205944 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6351530000 # Total ticks spent in databus transfers
system.physmem.avgQLat 24821.55 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgMemAccLat 43571.55 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.34 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.56 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.34 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.31 # Average write queue length when enqueuing
system.physmem.readRowHits 1047361 # Number of row buffer hits during reads
system.physmem.writeRowHits 815697 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.94 # Row buffer hit rate for writes
system.physmem.avgGap 21864788.20 # Average gap between requests
system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1828287720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 997577625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4889757600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3480388560 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1226219398425 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29718601656750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34308233025720 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.467372 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49439480717043 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713811840000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.memoryStateTime::ACT 170428636707 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.actEnergy 1810756080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 988011750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 5018598000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3479837760 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1228704019020 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29716422156750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34308639338400 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.475289 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49435820968594 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713811840000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::ACT 174088371406 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.lookups 225557622 # Number of BP lookups
system.cpu.branchPred.condPredicted 150824960 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12221670 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 159273353 # Number of BTB lookups
system.cpu.branchPred.BTBHits 104130221 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.BTBHitPct 65.378307 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 30957399 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 344598 # Number of incorrect RAS predictions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.walker.walks 199616 # Table walker walks requested
system.cpu.checker.dtb.walker.walksLong 199616 # Table walker walks initiated with long descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 199616 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 199616 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 199616 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples 1622408500 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 1622408500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 1622408500 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walkPageSizes::4K 155025 91.25% 91.25% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::2M 14865 8.75% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 169890 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 199616 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 199616 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169890 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169890 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 369506 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.read_hits 160527490 # DTB read hits
system.cpu.checker.dtb.read_misses 148526 # DTB read misses
system.cpu.checker.dtb.write_hits 145616651 # DTB write hits
system.cpu.checker.dtb.write_misses 51090 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 72318 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.prefetch_faults 7517 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.perms_faults 19125 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 160676016 # DTB read accesses
system.cpu.checker.dtb.write_accesses 145667741 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.dtb.hits 306144141 # DTB hits
system.cpu.checker.dtb.misses 199616 # DTB misses
system.cpu.checker.dtb.accesses 306343757 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.itb.walker.walks 120521 # Table walker walks requested
system.cpu.checker.itb.walker.walksLong 120521 # Table walker walks initiated with long descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 120521 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 120521 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 120521 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 1621807000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 1621807000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 1621807000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 108578 98.83% 98.83% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.17% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 109864 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120521 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120521 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109864 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109864 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 230385 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.inst_hits 853734937 # ITB inst hits
system.cpu.checker.itb.inst_misses 120521 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 52057 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.checker.itb.inst_accesses 853855458 # ITB inst accesses
system.cpu.checker.itb.hits 853734937 # DTB hits
system.cpu.checker.itb.misses 120521 # DTB misses
system.cpu.checker.itb.accesses 853855458 # DTB accesses
system.cpu.checker.numCycles 1003246954 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walks 951838 # Table walker walks requested
system.cpu.dtb.walker.walksLong 951838 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16475 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156308 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 435006 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 516832 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 1986.510123 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-32767 508349 98.36% 98.36% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-65535 5443 1.05% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-98303 1244 0.24% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::98304-131071 1085 0.21% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-163839 165 0.03% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::163840-196607 178 0.03% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-229375 121 0.02% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::229376-262143 54 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-294911 95 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::294912-327679 7 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-360447 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::360448-393215 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-425983 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::425984-458751 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 516832 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 485267 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 475094 97.90% 97.90% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 9290 1.91% 99.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 546 0.11% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 199 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 82 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 20 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walkCompletionTime::total 485267 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 776250627376 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.722476 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.519579 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 774163165376 99.73% 99.73% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 1120728500 0.14% 99.88% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 435636500 0.06% 99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 187638500 0.02% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 148036000 0.02% 99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 113935000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 26323500 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 52542500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 2621500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 776250627376 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 156309 90.46% 90.46% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 16475 9.54% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 172784 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951838 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951838 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172784 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172784 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1124622 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.read_hits 170417440 # DTB read hits
system.cpu.dtb.read_misses 677013 # DTB read misses
system.cpu.dtb.write_hits 148384109 # DTB write hits
system.cpu.dtb.write_misses 274825 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 72556 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 10696 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.perms_faults 70061 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 171094453 # DTB read accesses
system.cpu.dtb.write_accesses 148658934 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.hits 318801549 # DTB hits
system.cpu.dtb.misses 951838 # DTB misses
system.cpu.dtb.accesses 319753387 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walks 162167 # Table walker walks requested
system.cpu.itb.walker.walksLong 162167 # Table walker walks initiated with long descriptors
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walksLongTerminationLevel::Level3 122178 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 17760 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 144407 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1087.128740 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 7079.961036 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767 143546 99.40% 99.40% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535 491 0.34% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303 245 0.17% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071 86 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 144407 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 141371 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 27408.566821 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 138940 98.28% 98.28% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 2106 1.49% 99.77% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 209 0.15% 99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 62 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walkCompletionTime::total 141371 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 655988501088 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.936740 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.243710 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 41542191152 6.33% 6.33% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 614402729936 93.66% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 43110500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 467500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 655988501088 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 122178 98.84% 98.84% # Table walker page sizes translated
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walkPageSizes::total 123611 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162167 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 162167 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123611 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 123611 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 285778 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 358625455 # ITB inst hits
system.cpu.itb.inst_misses 162167 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.flush_tlb_mva_asid 79428 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 2050 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 53363 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.perms_faults 372145 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.inst_accesses 358787622 # ITB inst accesses
system.cpu.itb.hits 358625455 # DTB hits
system.cpu.itb.misses 162167 # DTB misses
system.cpu.itb.accesses 358787622 # DTB accesses
system.cpu.numCycles 1590418745 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.icacheStallCycles 646410999 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1006402404 # Number of instructions fetch has processed
system.cpu.fetch.Branches 225557622 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 135087620 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 866562323 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26107474 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 3678311 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 25439 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9275413 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1023850 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 676 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 358236204 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6112300 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 49056 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 1540030748 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.765724 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.157325 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.rateDist::0 979927440 63.63% 63.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 215057699 13.96% 77.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 70955696 4.61% 82.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 274089913 17.80% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.rateDist::total 1540030748 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.141823 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.632791 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 525466953 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 519947088 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 434864784 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 50506307 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9245616 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33796734 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 3867997 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1090931528 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 29050280 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9245616 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 570424085 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 50840114 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 363017689 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 440398811 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 106104433 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1071115355 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 6801917 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 5040663 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 343395 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 645255 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 54344412 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 20434 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1018974666 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1651092433 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1266893179 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1473696 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 953236782 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 65737881 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27206823 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23528426 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 103688094 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 174464093 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 151959443 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 9931077 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 9032567 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1035787653 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27506074 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1051526043 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3293799 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 60619533 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33780075 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 314140 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1540030748 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.682795 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.925415 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.issued_per_cycle::0 888949202 57.72% 57.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 336251490 21.83% 79.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 235798342 15.31% 94.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 72468185 4.71% 99.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6544331 0.42% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 19198 0.00% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.issued_per_cycle::total 1540030748 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::IntAlu 58035888 35.01% 35.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 99674 0.06% 35.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26738 0.02% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 574 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44566242 26.88% 61.97% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 63041416 38.03% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 724142674 68.87% 68.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2543730 0.24% 69.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 122779 0.01% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 376 0.00% 69.12% # Type of FU issued
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 121012 0.01% 69.13% # Type of FU issued
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::MemRead 174312709 16.58% 85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 150282706 14.29% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::total 1051526043 # Type of FU issued
system.cpu.iq.rate 0.661163 # Inst issue rate
system.cpu.iq.fu_busy_cnt 165770532 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157648 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3809671307 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1123107931 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1033541701 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2475857 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 947397 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 910004 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1215741366 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1555198 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 4333965 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 13839303 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14833 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 143349 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6338712 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2540349 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1552925 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewSquashCycles 9245616 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 6389360 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 5797347 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1063516239 # Number of instructions dispatched to IQ
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewDispLoadInsts 174464093 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 151959443 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 23100216 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 59008 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5663632 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 143349 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3667729 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 5111764 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8779493 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1040328227 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 170406440 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10257681 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.exec_nop 222512 # number of nop insts executed
system.cpu.iew.exec_refs 318786335 # number of memory reference insts executed
system.cpu.iew.exec_branches 197400349 # Number of branches executed
system.cpu.iew.exec_stores 148379895 # Number of stores executed
system.cpu.iew.exec_rate 0.654122 # Inst execution rate
system.cpu.iew.wb_sent 1035262700 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1034451705 # cumulative count of insts written-back
system.cpu.iew.wb_producers 440415620 # num instructions producing a value
system.cpu.iew.wb_consumers 712619707 # num instructions consuming a value
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.wb_rate 0.650427 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.618023 # average fanout of values written-back
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.commitSquashedInsts 51498978 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 27191934 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 8413549 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1528028900 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.656188 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.286676 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.committed_per_cycle::0 1013092181 66.30% 66.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 289858237 18.97% 85.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 121052617 7.92% 93.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 36682667 2.40% 95.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28563883 1.87% 97.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14105791 0.92% 98.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8655946 0.57% 98.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4198069 0.27% 99.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11819509 0.77% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.committed_per_cycle::total 1528028900 # Number of insts commited each cycle
system.cpu.commit.committedInsts 853325819 # Number of instructions committed
system.cpu.commit.committedOps 1002674190 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.refs 306245520 # Number of memory references committed
system.cpu.commit.loads 160624789 # Number of loads committed
system.cpu.commit.membars 6977905 # Number of memory barriers committed
system.cpu.commit.branches 190474151 # Number of branches committed
system.cpu.commit.fp_insts 896785 # Number of committed floating point instructions.
system.cpu.commit.int_insts 921116747 # Number of committed integer instructions.
system.cpu.commit.function_calls 25400785 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.op_class_0::IntAlu 694059947 69.22% 69.22% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2158876 0.22% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 98131 0.01% 69.45% # Class of committed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.op_class_0::SimdFloatMisc 111674 0.01% 69.46% # Class of committed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.op_class_0::MemRead 160624789 16.02% 85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 145620731 14.52% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.op_class_0::total 1002674190 # Class of committed instruction
system.cpu.commit.bw_lim_events 11819509 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2562796067 # The number of ROB reads
system.cpu.rob.rob_writes 2120254358 # The number of ROB writes
system.cpu.timesIdled 8129447 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 50387997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 101057024238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 853325819 # Number of Instructions Simulated
system.cpu.committedOps 1002674190 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.863788 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.863788 # CPI: Total CPI of All Threads
system.cpu.ipc 0.536542 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.536542 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1231590969 # number of integer regfile reads
system.cpu.int_regfile_writes 735370650 # number of integer regfile writes
system.cpu.fp_regfile_reads 1462122 # number of floating regfile reads
system.cpu.fp_regfile_writes 782688 # number of floating regfile writes
system.cpu.cc_regfile_reads 226859046 # number of cc regfile reads
system.cpu.cc_regfile_writes 227515194 # number of cc regfile writes
system.cpu.misc_regfile_reads 2534481060 # number of misc regfile reads
system.cpu.misc_regfile_writes 27245755 # number of misc regfile writes
system.cpu.dcache.tags.replacements 9758519 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.983709 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 284707567 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9759031 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.173754 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.983709 # Average occupied blocks per requestor
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.tag_accesses 1243872376 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1243872376 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 147964440 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147964440 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128940955 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128940955 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 380183 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 380183 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 324678 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 324678 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3327415 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3327415 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3725844 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3725844 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 276905395 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 276905395 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 277285578 # number of overall hits
system.cpu.dcache.overall_hits::total 277285578 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9612542 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9612542 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 11385353 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 11385353 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1184834 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1184834 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1232047 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1232047 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 450033 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 450033 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 20997895 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 20997895 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 22182729 # number of overall misses
system.cpu.dcache.overall_misses::total 22182729 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 144669003500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 330867751444 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 63675897168 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 63675897168 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6433485000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 6433485000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 475536754944 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 475536754944 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 475536754944 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 475536754944 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 157576982 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 157576982 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 140326308 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 140326308 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1565017 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1565017 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1556725 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1556725 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3777448 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3777448 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3725851 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3725851 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 297903290 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 297903290 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 299468307 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 299468307 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061002 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.061002 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081135 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.081135 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757074 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.757074 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791435 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.791435 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119137 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119137 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.070486 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.070486 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074074 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074074 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35857.142857 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35857.142857 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22646.877458 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21437.252150 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 35158879 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked::no_mshrs 1606955 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.879193 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.writebacks::writebacks 7549082 # number of writebacks
system.cpu.dcache.writebacks::total 7549082 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4467834 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4467834 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9360902 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9360902 # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7079 # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total 7079 # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219205 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 219205 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 13828736 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 13828736 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 13828736 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 13828736 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5144708 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5144708 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2024451 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2024451 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1178103 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1178103 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224968 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1224968 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230828 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 230828 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 7169159 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 7169159 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8347262 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8347262 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75818409500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75818409500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57062160713 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57062160713 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20148080000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20148080000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 62191648168 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 62191648168 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3063087000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3063087000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 132880570213 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 153028650213 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5828327500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5828327500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5707957967 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5707957967 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11536285467 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11536285467 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032649 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032649 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014427 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014427 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752773 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752773 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786888 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786888 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061107 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061107 # mshr miss rate for LoadLockedReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024065 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.024065 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027874 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.027874 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.replacements 15042093 # number of replacements
system.cpu.icache.tags.tagsinuse 511.944879 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 342405629 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15042605 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22.762389 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.944879 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999892 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.tag_accesses 373257734 # Number of tag accesses
system.cpu.icache.tags.data_accesses 373257734 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 342405629 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 342405629 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 342405629 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 342405629 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 342405629 # number of overall hits
system.cpu.icache.overall_hits::total 342405629 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15809279 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15809279 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15809279 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15809279 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15809279 # number of overall misses
system.cpu.icache.overall_misses::total 15809279 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 208403044384 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 208403044384 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 208403044384 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 208403044384 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 208403044384 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 358214908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 358214908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 358214908 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 358214908 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 358214908 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 358214908 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044134 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.044134 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.044134 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.044134 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.044134 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.044134 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13182.324405 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13182.324405 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 15030 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.blocked::no_mshrs 1210 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 12.421488 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766453 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 766453 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 766453 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 766453 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 766453 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 766453 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15042826 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15042826 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15042826 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15042826 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15042826 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15042826 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 186915451392 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 186915451392 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 1594412000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041994 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.041994 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.041994 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.replacements 1148683 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65278.817014 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 46198537 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1210914 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 38.151790 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 15659706000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 301.460755 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 460.210435 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7626.713626 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.567520 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004600 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007022 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116374 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.300560 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996076 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 380 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61851 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 379 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2690 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5173 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53395 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943771 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 410382726 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 410382726 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 788948 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299798 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1088746 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 7549082 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 7549082 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9455 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 9455 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1576072 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1576072 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14958434 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 14958434 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6296354 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6296354 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 732370 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 732370 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 788948 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 299798 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14958434 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7872426 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 23919606 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 788948 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 299798 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14958434 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7872426 # number of overall hits
system.cpu.l2cache.overall_hits::total 23919606 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3175 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2963 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 6138 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 34552 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 34552 # number of UpgradeReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 407912 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 407912 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 84184 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 84184 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 253746 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 253746 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 492598 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 492598 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 3175 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2963 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 84184 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 661658 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 751980 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 3175 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2963 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 84184 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 661658 # number of overall misses
system.cpu.l2cache.overall_misses::total 751980 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276956000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 265379500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 542335500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 544075000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 544075000 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36032836500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 36032836500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7082572500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 7082572500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22536354000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 22536354000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 51203919000 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 51203919000 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276956000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 265379500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 7082572500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 58569190500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 66194098500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276956000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 265379500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 7082572500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 58569190500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 66194098500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 792123 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302761 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1094884 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 7549082 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 7549082 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44007 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 44007 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1983984 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1983984 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15042618 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15042618 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6550100 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 6550100 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1224968 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1224968 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 792123 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 302761 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 15042618 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 8534084 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 24671586 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 792123 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 302761 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15042618 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 8534084 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 24671586 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004008 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009787 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.005606 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785148 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.785148 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205602 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.205602 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005596 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005596 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.038739 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.038739 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.402131 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.402131 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004008 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009787 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005596 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.077531 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.030480 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004008 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009787 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005596 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.077531 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.030480 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87230.236220 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89564.461694 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 88357.038123 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15746.555916 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15746.555916 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88334.828345 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88334.828345 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84132.050033 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88814.617767 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88814.617767 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 103946.664420 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 103946.664420 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 88026.408282 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.writebacks::writebacks 967181 # number of writebacks
system.cpu.l2cache.writebacks::total 967181 # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3175 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2963 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 6138 # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1073 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1073 # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34552 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 34552 # number of UpgradeReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 407912 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 407912 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 84184 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 84184 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 253725 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 253725 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 492598 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 492598 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3175 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2963 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 84184 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 661637 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 751959 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3175 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2963 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84184 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 661637 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 751959 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54973 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88669 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 245206000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 235749500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 480955500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 717374500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 717374500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 161500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 161500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31953716500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31953716500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6240732500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6240732500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19997854000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19997854000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 46277939000 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 46277939000 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 245206000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 235749500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6240732500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51951570500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 58673258500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 245206000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 235749500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6240732500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51951570500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 58673258500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1328224500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407344500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6735569000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5315951000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5315951000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1328224500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10723295500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12051520000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005606 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785148 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785148 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205602 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205602 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005596 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038736 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038736 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.402131 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.402131 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.030479 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.030479 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62372.599202 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 1633565 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23227278 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 8622904 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 17438576 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 44010 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 44017 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1983984 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1983984 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15042826 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6558947 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1331632 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1224968 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45167572 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29499463 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 732865 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1940611 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 77340511 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 963068272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1029563294 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2422088 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6336984 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2001390638 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1864369 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 52693428 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.056141 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.230194 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 49735173 94.39% 94.39% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 2958255 5.61% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::total 52693428 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 33222815494 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1182000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 22592032956 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 13487423434 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 430634727 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 1148958035 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer27.occupancy 568813596 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.replacements 115455 # number of replacements
system.iocache.tags.tagsinuse 10.423947 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.warmup_cycle 13095311635000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544418 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.879529 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429971 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651497 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.tag_accesses 1039623 # Number of tag accesses
system.iocache.tags.data_accesses 1039623 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses
system.iocache.demand_misses::total 8850 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_misses::realview.ide 8810 # number of overall misses
system.iocache.overall_misses::total 8850 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1621911166 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1626980166 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12610487430 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12610487430 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1621911166 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1627331166 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1621911166 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1627331166 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_accesses::realview.ide 8810 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8850 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_accesses::realview.ide 8810 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8850 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 183901.906409 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183879.227797 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183879.227797 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 31681 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.blocked::no_mshrs 3345 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.471151 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_mshr_misses::realview.ide 8810 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8850 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_mshr_misses::realview.ide 8810 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8850 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1181411166 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1184630166 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277287430 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7277287430 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1181411166 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1184831166 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1181411166 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1184831166 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 54973 # Transaction distribution
system.membus.trans_dist::ReadResp 407867 # Transaction distribution
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
system.membus.trans_dist::WriteResp 33696 # Transaction distribution
system.membus.trans_dist::Writeback 1073811 # Transaction distribution
system.membus.trans_dist::CleanEvict 187846 # Transaction distribution
system.membus.trans_dist::UpgradeReq 35358 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::UpgradeResp 35361 # Transaction distribution
system.membus.trans_dist::ReadExReq 899707 # Transaction distribution
system.membus.trans_dist::ReadExResp 899707 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 352894 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3753956 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3883578 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 341714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4225292 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 141818700 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 141988686 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7244096 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7244096 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 149232782 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2955 # Total snoops (count)
system.membus.snoop_fanout::samples 2747442 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::1 2747442 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::total 2747442 # Request fanout histogram
system.membus.reqLayer0.occupancy 104159500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer2.occupancy 5443500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer5.occupancy 7279924206 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer2.occupancy 6776038462 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer3.occupancy 228860056 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.kern.inst.quiesce 16150 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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