2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-04-22 19:18:51 +02:00
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host_inst_rate 137427 # Simulator instruction rate (inst/s)
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host_mem_usage 350244 # Number of bytes of host memory used
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host_seconds 663.99 # Real time elapsed on the host
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host_tick_rate 67463360 # Simulator tick rate (ticks/s)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-04-04 18:42:31 +02:00
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sim_insts 91249905 # Number of instructions simulated
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sim_seconds 0.044795 # Number of seconds simulated
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sim_ticks 44794736000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-04-04 18:42:31 +02:00
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system.cpu.BPredUnit.BTBHits 24857865 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 26546272 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 12880 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 1596208 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 23792873 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 29586235 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 63032 # Number of times the RAS was used to get a target.
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system.cpu.commit.branchMispredicts 1599456 # The number of times a branch was mispredicted
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.branches 18722470 # Number of branches committed
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system.cpu.commit.bw_lim_events 671558 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 37771309 # The number of squashed insts skipped by commit
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::samples 84101876 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 1.085142 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::total 84101876 # Number of insts commited each cycle
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system.cpu.commit.count 91262514 # Number of instructions committed
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system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 56148 # Number of function calls committed.
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system.cpu.commit.int_insts 72533318 # Number of committed integer instructions.
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system.cpu.commit.loads 22575876 # Number of loads committed
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system.cpu.commit.membars 3888 # Number of memory barriers committed
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system.cpu.commit.refs 27322629 # Number of memory references committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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2011-04-04 18:42:31 +02:00
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system.cpu.committedInsts 91249905 # Number of Instructions Simulated
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system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated
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system.cpu.cpi 0.981803 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.981803 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 6763 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_hits 6756 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 123500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.001035 # miss rate for LoadLockedReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.ReadReq_accesses 24496209 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 5358.863391 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2291.343120 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 23475471 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5469995500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.041669 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1020738 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 105235 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 2097731500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.037373 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 915503 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 5796 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 5796 # number of StoreCondReq hits
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 26966.230972 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 29153.525857 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 4581642 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 4134974891 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.032384 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 153339 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 118609 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 1012501953 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.007335 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 34730 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 2888.334667 # average number of cycles each access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.avg_refs 29.539803 # Average number of references to valid blocks.
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.blocked::no_mshrs 7497 # number of cycles access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 21653845 # number of cycles access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.demand_accesses 29231190 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 8180.869220 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 28057113 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 9604970391 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.040165 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1174077 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 223844 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3110233453 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.032508 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 950233 # number of demand (read+write) MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.occ_blocks::0 3493.184851 # Average occupied blocks per context
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2011-04-20 03:45:23 +02:00
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system.cpu.dcache.occ_percent::0 0.852828 # Average percentage of cache occupancy
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.overall_accesses 29231190 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 8180.869220 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.overall_hits 28057113 # number of overall hits
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system.cpu.dcache.overall_miss_latency 9604970391 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.040165 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1174077 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 223844 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3110233453 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.032508 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 950233 # number of overall MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.replacements 946136 # number of replacements
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system.cpu.dcache.sampled_refs 950232 # Sample count of references to valid blocks.
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.tagsinuse 3493.184851 # Cycle average of tags in use
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system.cpu.dcache.total_refs 28069666 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 18896443000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 943153 # number of writebacks
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2011-04-20 03:45:23 +02:00
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system.cpu.decode.BlockedCycles 17588781 # Number of cycles decode is blocked
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system.cpu.decode.BranchMispred 9537 # Number of times decode detected a branch misprediction
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system.cpu.decode.BranchResolved 4762375 # Number of times decode resolved a branch
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system.cpu.decode.DecodedInsts 139874563 # Number of instructions handled by decode
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system.cpu.decode.IdleCycles 32956661 # Number of cycles decode is idle
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system.cpu.decode.RunCycles 32742845 # Number of cycles decode is running
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system.cpu.decode.SquashCycles 5457924 # Number of cycles decode is squashing
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system.cpu.decode.SquashedInsts 30438 # Number of squashed instructions handled by decode
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system.cpu.decode.UnblockCycles 813588 # Number of cycles decode is unblocking
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-04-04 18:42:31 +02:00
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system.cpu.fetch.Branches 29586235 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 15336543 # Number of cache lines fetched
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system.cpu.fetch.Cycles 34444061 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 252596 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 142085293 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 1618878 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.330242 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 15336543 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 24920897 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.585960 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 89559799 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.598579 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.586276 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-04-04 18:42:31 +02:00
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system.cpu.fetch.rateDist::0 55181021 61.61% 61.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 6379280 7.12% 68.74% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 6413392 7.16% 75.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4415439 4.93% 80.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 3489859 3.90% 84.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1871095 2.09% 86.81% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1928131 2.15% 88.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3220363 3.60% 92.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 6661219 7.44% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.fetch.rateDist::total 89559799 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fp_regfile_reads 96 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 96 # number of floating regfile writes
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 15336543 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35886.138614 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34397.626113 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 15335735 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 28996000 # number of ReadReq miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000053 # miss rate for ReadReq accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 134 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 23184000 # number of ReadReq MSHR miss cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000044 # mshr miss rate for ReadReq accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 674 # number of ReadReq MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.avg_refs 22787.124814 # Average number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.demand_accesses 15336543 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35886.138614 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 15335735 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 28996000 # number of demand (read+write) miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000053 # miss rate for demand accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 134 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 23184000 # number of demand (read+write) MSHR miss cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000044 # mshr miss rate for demand accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 674 # number of demand (read+write) MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 568.356083 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.icache.occ_percent::0 0.277518 # Average percentage of cache occupancy
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_accesses 15336543 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35886.138614 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_hits 15335735 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 28996000 # number of overall miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.000053 # miss rate for overall accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_misses 808 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 134 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 23184000 # number of overall MSHR miss cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000044 # mshr miss rate for overall accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 674 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.replacements 2 # number of replacements
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.tagsinuse 568.356083 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 15335735 # Total number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.idleCycles 29674 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.branchMispredicts 1809783 # Number of branch mispredicts detected at execute
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.exec_branches 20951910 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_nop 39919 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.157669 # Inst execution rate
|
|
|
|
|
system.cpu.iew.exec_refs 30258239 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_stores 5196792 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 316819 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 31496278 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 689079 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 358280 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 6614347 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 129035403 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 25061447 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 2046229 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 103714956 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 173808 # Number of times the IQ has become full, causing a stall
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 187 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 5457924 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 196064 # Number of cycles IEW is unblocking
|
2011-04-22 19:18:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 21877 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 398676 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 24099 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14224 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 8920401 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 1867594 # Number of stores squashed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.wb_consumers 127150055 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_count 102173263 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_fanout 0.489247 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_producers 62207806 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_rate 1.140461 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_sent 102563540 # cumulative count of insts sent to commit
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.int_regfile_reads 259728905 # number of integer regfile reads
|
2011-04-12 22:09:20 +02:00
|
|
|
system.cpu.int_regfile_writes 80595212 # number of integer regfile writes
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.ipc 1.018534 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.018534 # IPC: Total IPC of All Threads
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 105761185 # Type of FU issued
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_busy_cnt 177153 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 105938228 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 301287282 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 102173164 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 166475031 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 128301553 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 105761185 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 693931 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 37472339 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 28176 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 139525 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 69343981 # Number of squashed operands that are examined and possibly removed from graph
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 89559799 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 1.180900 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::total 89559799 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.rate 1.180509 # Inst issue rate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 34765 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34227.938648 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.585872 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 20226 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 497640000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.418208 # miss rate for ReadExReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451270000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.418208 # mshr miss rate for ReadExReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 916140 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34309.334657 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.709419 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 915133 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 34549500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.001099 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1007 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 31042500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001089 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 943153 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 943153 # number of Writeback hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.avg_refs 104.893699 # Average number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 950905 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34233.211115 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 935359 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 532189500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.016349 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 482312500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.016339 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 15537 # number of demand (read+write) MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 405.690928 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 8192.856570 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.l2cache.occ_percent::0 0.012381 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.250026 # Average percentage of cache occupancy
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 950905 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34233.211115 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.overall_hits 935359 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 532189500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.016349 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 15546 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 482312500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.016339 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 15537 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.replacements 702 # number of replacements
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 15522 # Sample count of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 8598.547498 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1628160 # Total number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 32 # number of writebacks
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 672298 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 377389 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 31496278 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 6614347 # Number of stores inserted to the mem dependence unit.
|
2011-04-12 22:09:20 +02:00
|
|
|
system.cpu.misc_regfile_reads 197340644 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 11602 # number of misc regfile writes
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.numCycles 89589473 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.rename.BlockCycles 2558009 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.CommittedMaps 71576967 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.IQFullEvents 2891853 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.IdleCycles 35560664 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RenameLookups 350271207 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RenamedInsts 135568411 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RenamedOperands 105865304 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RunCycles 30904016 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.SquashCycles 5457924 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.UnblockCycles 5891977 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.UndoneMaps 34288334 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 787 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.int_rename_lookups 350270420 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.serializingInsts 701223 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 13035103 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 702184 # count of temporary serializing insts renamed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.rob.rob_reads 212458407 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 263525841 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1433 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
