2007-04-22 20:39:39 +02:00
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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2006-08-16 20:42:44 +02:00
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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import m5
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from m5.objects import *
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class MyCache(BaseCache):
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assoc = 2
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block_size = 64
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2007-05-11 00:24:48 +02:00
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latency = '1ns'
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2006-08-16 20:42:44 +02:00
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mshrs = 10
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tgts_per_mshr = 5
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2011-03-18 01:20:19 +01:00
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class MyL1Cache(MyCache):
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is_top_level = True
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2006-10-08 19:53:24 +02:00
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cpu = TimingSimpleCPU(cpu_id=0)
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2011-03-18 01:20:19 +01:00
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cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
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MyL1Cache(size = '256kB'),
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2007-05-11 00:24:48 +02:00
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MyCache(size = '2MB', latency='10ns'))
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2006-08-16 20:42:44 +02:00
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system = System(cpu = cpu,
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2012-04-06 19:46:31 +02:00
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physmem = SimpleMemory(),
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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membus = CoherentBus())
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2012-02-13 12:43:09 +01:00
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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2012-03-02 15:21:48 +01:00
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# create the interrupt controller
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cpu.createInterruptController()
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2011-02-04 05:23:00 +01:00
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cpu.connectAllPorts(system.membus)
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2007-04-22 20:39:39 +02:00
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cpu.clock = '2GHz'
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2006-08-16 20:42:44 +02:00
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2012-01-28 16:24:34 +01:00
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root = Root(full_system=False, system = system)
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