2006-08-16 20:45:12 +02:00
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---------- Begin Simulation Statistics ----------
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2007-04-22 20:50:37 +02:00
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sim_seconds 0.000001 # Number of seconds simulated
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2007-08-27 05:27:53 +02:00
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sim_ticks 1297500 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 182014 # Simulator instruction rate (inst/s)
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host_tick_rate 91451888 # Simulator tick rate (ticks/s)
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host_mem_usage 197324 # Number of bytes of host memory used
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host_seconds 0.01 # Real time elapsed on the host
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sim_insts 2577 # Number of instructions simulated
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system.physmem.bytes_read 13356 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 2058 # Number of bytes written to this memory
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system.physmem.num_reads 3000 # Number of read requests responded to by this memory
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system.physmem.num_writes 294 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 10293641618 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 7969171484 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 1586127168 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 11879768786 # Total bandwidth to/from this memory (bytes/s)
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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2007-08-27 05:27:53 +02:00
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system.cpu.dtb.read_hits 415 # DTB read hits
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system.cpu.dtb.read_misses 4 # DTB read misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 419 # DTB read accesses
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2007-08-27 05:27:53 +02:00
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system.cpu.dtb.write_hits 294 # DTB write hits
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system.cpu.dtb.write_misses 4 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 298 # DTB write accesses
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system.cpu.dtb.data_hits 709 # DTB hits
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system.cpu.dtb.data_misses 8 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 717 # DTB accesses
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2009-04-09 07:21:30 +02:00
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system.cpu.itb.fetch_hits 2585 # ITB hits
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system.cpu.itb.fetch_misses 11 # ITB misses
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2012-01-25 18:19:50 +01:00
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 2596 # ITB accesses
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2009-04-09 07:21:30 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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2012-01-25 18:19:50 +01:00
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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2009-04-09 07:21:30 +02:00
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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2007-08-27 05:27:53 +02:00
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system.cpu.numCycles 2596 # number of cpu cycles simulated
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2011-02-08 04:23:13 +01:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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2012-01-25 18:19:50 +01:00
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2007-08-27 05:27:53 +02:00
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system.cpu.num_insts 2577 # Number of instructions executed
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2011-02-08 04:23:13 +01:00
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system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
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system.cpu.num_func_calls 140 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
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2011-02-08 04:23:13 +01:00
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system.cpu.num_int_insts 2375 # number of integer instructions
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_insts 6 # number of float instructions
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2011-02-08 04:23:13 +01:00
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system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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2011-02-08 04:23:13 +01:00
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system.cpu.num_mem_refs 717 # number of memory refs
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2012-01-25 18:19:50 +01:00
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system.cpu.num_load_insts 419 # Number of load instructions
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2011-02-08 04:23:13 +01:00
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system.cpu.num_store_insts 298 # Number of store instructions
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2012-01-25 18:19:50 +01:00
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 2596 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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2006-08-16 20:45:12 +02:00
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---------- End Simulation Statistics ----------
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