2010-06-02 19:58:05 +02:00
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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svcCode = '''
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#if FULL_SYSTEM
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fault = new SupervisorCall;
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#else
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fault = new SupervisorCall(machInst);
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#endif
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'''
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svcIop = InstObjParams("svc", "Svc", "PredOp",
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{ "code": svcCode,
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"predicate_test": predicateTest }, ["IsSyscall"])
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header_output = BasicDeclare.subst(svcIop)
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decoder_output = BasicConstructor.subst(svcIop)
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exec_output = PredOpExecute.subst(svcIop)
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}};
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2010-06-02 19:58:05 +02:00
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let {{
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header_output = decoder_output = exec_output = ""
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mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
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mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
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{ "code": mrsCpsrCode,
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"predicate_test": predicateTest }, [])
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header_output += MrsDeclare.subst(mrsCpsrIop)
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decoder_output += MrsConstructor.subst(mrsCpsrIop)
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exec_output += PredOpExecute.subst(mrsCpsrIop)
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mrsSpsrCode = "Dest = Spsr"
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mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
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{ "code": mrsSpsrCode,
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"predicate_test": predicateTest }, [])
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header_output += MrsDeclare.subst(mrsSpsrIop)
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decoder_output += MrsConstructor.subst(mrsSpsrIop)
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exec_output += PredOpExecute.subst(mrsSpsrIop)
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msrCpsrRegCode = '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
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{ "code": msrCpsrRegCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrRegDeclare.subst(msrCpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
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exec_output += PredOpExecute.subst(msrCpsrRegIop)
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msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
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msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
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{ "code": msrSpsrRegCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrRegDeclare.subst(msrSpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
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exec_output += PredOpExecute.subst(msrSpsrRegIop)
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msrCpsrImmCode = '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
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{ "code": msrCpsrImmCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrImmDeclare.subst(msrCpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
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exec_output += PredOpExecute.subst(msrCpsrImmIop)
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msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
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msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
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{ "code": msrSpsrImmCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrImmDeclare.subst(msrSpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
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exec_output += PredOpExecute.subst(msrSpsrImmIop)
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2010-06-02 19:58:05 +02:00
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revCode = '''
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uint32_t val = Op1;
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Dest = swap_byte(val);
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'''
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revIop = InstObjParams("rev", "Rev", "RevOp",
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{ "code": revCode,
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"predicate_test": predicateTest }, [])
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header_output += RevOpDeclare.subst(revIop)
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decoder_output += RevOpConstructor.subst(revIop)
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exec_output += PredOpExecute.subst(revIop)
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rev16Code = '''
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uint32_t val = Op1;
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Dest = (bits(val, 15, 8) << 0) |
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(bits(val, 7, 0) << 8) |
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(bits(val, 31, 24) << 16) |
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(bits(val, 23, 16) << 24);
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'''
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rev16Iop = InstObjParams("rev16", "Rev16", "RevOp",
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{ "code": rev16Code,
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"predicate_test": predicateTest }, [])
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header_output += RevOpDeclare.subst(rev16Iop)
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decoder_output += RevOpConstructor.subst(rev16Iop)
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exec_output += PredOpExecute.subst(rev16Iop)
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revshCode = '''
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uint16_t val = Op1;
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Dest = sext<16>(swap_byte(val));
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'''
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revshIop = InstObjParams("revsh", "Revsh", "RevOp",
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{ "code": revshCode,
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"predicate_test": predicateTest }, [])
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header_output += RevOpDeclare.subst(revshIop)
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decoder_output += RevOpConstructor.subst(revshIop)
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exec_output += PredOpExecute.subst(revshIop)
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2010-06-02 19:58:06 +02:00
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ssatCode = '''
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int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
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int32_t res;
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2010-06-02 19:58:07 +02:00
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if (satInt(res, operand, imm))
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2010-06-02 19:58:06 +02:00
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CondCodes = CondCodes | (1 << 27);
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else
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CondCodes = CondCodes;
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Dest = res;
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'''
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2010-06-02 19:58:07 +02:00
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ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
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2010-06-02 19:58:06 +02:00
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{ "code": ssatCode,
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"predicate_test": predicateTest }, [])
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2010-06-02 19:58:07 +02:00
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header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
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decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
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2010-06-02 19:58:06 +02:00
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exec_output += PredOpExecute.subst(ssatIop)
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usatCode = '''
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int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
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int32_t res;
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2010-06-02 19:58:07 +02:00
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if (uSatInt(res, operand, imm))
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2010-06-02 19:58:06 +02:00
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CondCodes = CondCodes | (1 << 27);
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else
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CondCodes = CondCodes;
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Dest = res;
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'''
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2010-06-02 19:58:07 +02:00
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usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
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2010-06-02 19:58:06 +02:00
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{ "code": usatCode,
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"predicate_test": predicateTest }, [])
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2010-06-02 19:58:07 +02:00
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header_output += RegImmRegShiftOpDeclare.subst(usatIop)
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decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
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2010-06-02 19:58:06 +02:00
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exec_output += PredOpExecute.subst(usatIop)
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ssat16Code = '''
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int32_t res;
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uint32_t resTemp = 0;
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CondCodes = CondCodes;
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int32_t argLow = sext<16>(bits(Op1, 15, 0));
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int32_t argHigh = sext<16>(bits(Op1, 31, 16));
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2010-06-02 19:58:07 +02:00
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if (satInt(res, argLow, imm))
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2010-06-02 19:58:06 +02:00
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CondCodes = CondCodes | (1 << 27);
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replaceBits(resTemp, 15, 0, res);
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2010-06-02 19:58:07 +02:00
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if (satInt(res, argHigh, imm))
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2010-06-02 19:58:06 +02:00
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CondCodes = CondCodes | (1 << 27);
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replaceBits(resTemp, 31, 16, res);
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Dest = resTemp;
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'''
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2010-06-02 19:58:07 +02:00
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ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
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2010-06-02 19:58:06 +02:00
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{ "code": ssat16Code,
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"predicate_test": predicateTest }, [])
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2010-06-02 19:58:07 +02:00
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header_output += RegImmRegOpDeclare.subst(ssat16Iop)
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decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
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2010-06-02 19:58:06 +02:00
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exec_output += PredOpExecute.subst(ssat16Iop)
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usat16Code = '''
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int32_t res;
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uint32_t resTemp = 0;
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CondCodes = CondCodes;
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int32_t argLow = sext<16>(bits(Op1, 15, 0));
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int32_t argHigh = sext<16>(bits(Op1, 31, 16));
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2010-06-02 19:58:07 +02:00
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if (uSatInt(res, argLow, imm))
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2010-06-02 19:58:06 +02:00
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CondCodes = CondCodes | (1 << 27);
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replaceBits(resTemp, 15, 0, res);
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2010-06-02 19:58:07 +02:00
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if (uSatInt(res, argHigh, imm))
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2010-06-02 19:58:06 +02:00
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CondCodes = CondCodes | (1 << 27);
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replaceBits(resTemp, 31, 16, res);
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Dest = resTemp;
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'''
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2010-06-02 19:58:07 +02:00
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usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
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2010-06-02 19:58:06 +02:00
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{ "code": usat16Code,
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"predicate_test": predicateTest }, [])
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2010-06-02 19:58:07 +02:00
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header_output += RegImmRegOpDeclare.subst(usat16Iop)
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decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
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2010-06-02 19:58:06 +02:00
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exec_output += PredOpExecute.subst(usat16Iop)
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2010-06-02 19:58:07 +02:00
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sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
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{ "code":
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"Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxtbIop)
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decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
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exec_output += PredOpExecute.subst(sxtbIop)
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sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
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{ "code":
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'''
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Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
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Op1;
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''',
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
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decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
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exec_output += PredOpExecute.subst(sxtabIop)
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sxtb16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
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replaceBits(resTemp, 31, 16,
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sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
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Dest = resTemp;
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'''
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sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
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{ "code": sxtb16Code,
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"predicate_test": predicateTest }, [])
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header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
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decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
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exec_output += PredOpExecute.subst(sxtb16Iop)
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sxtab16Code = '''
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uint32_t resTemp = 0;
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replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
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bits(Op1, 15, 0));
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replaceBits(resTemp, 31, 16,
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sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
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bits(Op1, 31, 16));
|
|
|
|
|
Dest = resTemp;
|
|
|
|
|
'''
|
|
|
|
|
sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
|
|
|
|
|
{ "code": sxtab16Code,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
|
|
|
|
|
decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
|
|
|
|
|
exec_output += PredOpExecute.subst(sxtab16Iop)
|
|
|
|
|
|
|
|
|
|
sxthCode = '''
|
|
|
|
|
uint64_t rotated = (uint32_t)Op1;
|
|
|
|
|
rotated = (rotated | (rotated << 32)) >> imm;
|
|
|
|
|
Dest = sext<16>((uint16_t)rotated);
|
|
|
|
|
'''
|
|
|
|
|
sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
|
|
|
|
|
{ "code": sxthCode,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegImmRegOpDeclare.subst(sxthIop)
|
|
|
|
|
decoder_output += RegImmRegOpConstructor.subst(sxthIop)
|
|
|
|
|
exec_output += PredOpExecute.subst(sxthIop)
|
|
|
|
|
|
|
|
|
|
sxtahCode = '''
|
|
|
|
|
uint64_t rotated = (uint32_t)Op2;
|
|
|
|
|
rotated = (rotated | (rotated << 32)) >> imm;
|
|
|
|
|
Dest = sext<16>((uint16_t)rotated) + Op1;
|
|
|
|
|
'''
|
|
|
|
|
sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
|
|
|
|
|
{ "code": sxtahCode,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
|
|
|
|
|
decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
|
|
|
|
|
exec_output += PredOpExecute.subst(sxtahIop)
|
|
|
|
|
|
|
|
|
|
uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
|
|
|
|
|
{ "code": "Dest = (uint8_t)(Op1.ud >> imm);",
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegImmRegOpDeclare.subst(uxtbIop)
|
|
|
|
|
decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
|
|
|
|
|
exec_output += PredOpExecute.subst(uxtbIop)
|
|
|
|
|
|
|
|
|
|
uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
|
|
|
|
|
{ "code":
|
|
|
|
|
"Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
|
|
|
|
|
decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
|
|
|
|
|
exec_output += PredOpExecute.subst(uxtabIop)
|
|
|
|
|
|
|
|
|
|
uxtb16Code = '''
|
|
|
|
|
uint32_t resTemp = 0;
|
|
|
|
|
replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
|
|
|
|
|
replaceBits(resTemp, 31, 16,
|
|
|
|
|
(uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
|
|
|
|
|
Dest = resTemp;
|
|
|
|
|
'''
|
|
|
|
|
uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
|
|
|
|
|
{ "code": uxtb16Code,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
|
|
|
|
|
decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
|
|
|
|
|
exec_output += PredOpExecute.subst(uxtb16Iop)
|
|
|
|
|
|
|
|
|
|
uxtab16Code = '''
|
|
|
|
|
uint32_t resTemp = 0;
|
|
|
|
|
replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
|
|
|
|
|
bits(Op1, 15, 0));
|
|
|
|
|
replaceBits(resTemp, 31, 16,
|
|
|
|
|
(uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
|
|
|
|
|
bits(Op1, 31, 16));
|
|
|
|
|
Dest = resTemp;
|
|
|
|
|
'''
|
|
|
|
|
uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
|
|
|
|
|
{ "code": uxtab16Code,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
|
|
|
|
|
decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
|
|
|
|
|
exec_output += PredOpExecute.subst(uxtab16Iop)
|
|
|
|
|
|
|
|
|
|
uxthCode = '''
|
|
|
|
|
uint64_t rotated = (uint32_t)Op1;
|
|
|
|
|
rotated = (rotated | (rotated << 32)) >> imm;
|
|
|
|
|
Dest = (uint16_t)rotated;
|
|
|
|
|
'''
|
|
|
|
|
uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
|
|
|
|
|
{ "code": uxthCode,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegImmRegOpDeclare.subst(uxthIop)
|
|
|
|
|
decoder_output += RegImmRegOpConstructor.subst(uxthIop)
|
|
|
|
|
exec_output += PredOpExecute.subst(uxthIop)
|
|
|
|
|
|
|
|
|
|
uxtahCode = '''
|
|
|
|
|
uint64_t rotated = (uint32_t)Op2;
|
|
|
|
|
rotated = (rotated | (rotated << 32)) >> imm;
|
|
|
|
|
Dest = (uint16_t)rotated + Op1;
|
|
|
|
|
'''
|
|
|
|
|
uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
|
|
|
|
|
{ "code": uxtahCode,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
|
|
|
|
|
decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
|
|
|
|
|
exec_output += PredOpExecute.subst(uxtahIop)
|
2010-06-02 19:58:07 +02:00
|
|
|
|
|
|
|
|
selCode = '''
|
|
|
|
|
uint32_t resTemp = 0;
|
|
|
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
|
|
|
int low = i * 8;
|
|
|
|
|
int high = low + 7;
|
|
|
|
|
replaceBits(resTemp, high, low,
|
|
|
|
|
bits(CondCodes, 16 + i) ?
|
|
|
|
|
bits(Op1, high, low) : bits(Op2, high, low));
|
|
|
|
|
}
|
|
|
|
|
Dest = resTemp;
|
|
|
|
|
'''
|
|
|
|
|
selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
|
|
|
|
|
{ "code": selCode,
|
|
|
|
|
"predicate_test": predicateTest }, [])
|
|
|
|
|
header_output += RegRegRegOpDeclare.subst(selIop)
|
|
|
|
|
decoder_output += RegRegRegOpConstructor.subst(selIop)
|
|
|
|
|
exec_output += PredOpExecute.subst(selIop)
|
2010-06-02 19:58:05 +02:00
|
|
|
}};
|
