2010-06-02 19:58:05 +02:00
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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svcCode = '''
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#if FULL_SYSTEM
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fault = new SupervisorCall;
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#else
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fault = new SupervisorCall(machInst);
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#endif
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'''
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svcIop = InstObjParams("svc", "Svc", "PredOp",
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{ "code": svcCode,
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"predicate_test": predicateTest }, ["IsSyscall"])
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header_output = BasicDeclare.subst(svcIop)
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decoder_output = BasicConstructor.subst(svcIop)
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exec_output = PredOpExecute.subst(svcIop)
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}};
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2010-06-02 19:58:05 +02:00
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let {{
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header_output = decoder_output = exec_output = ""
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mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
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mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
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{ "code": mrsCpsrCode,
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"predicate_test": predicateTest }, [])
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header_output += MrsDeclare.subst(mrsCpsrIop)
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decoder_output += MrsConstructor.subst(mrsCpsrIop)
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exec_output += PredOpExecute.subst(mrsCpsrIop)
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mrsSpsrCode = "Dest = Spsr"
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mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
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{ "code": mrsSpsrCode,
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"predicate_test": predicateTest }, [])
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header_output += MrsDeclare.subst(mrsSpsrIop)
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decoder_output += MrsConstructor.subst(mrsSpsrIop)
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exec_output += PredOpExecute.subst(mrsSpsrIop)
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msrCpsrRegCode = '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
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{ "code": msrCpsrRegCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrRegDeclare.subst(msrCpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
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exec_output += PredOpExecute.subst(msrCpsrRegIop)
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msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
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msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
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{ "code": msrSpsrRegCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrRegDeclare.subst(msrSpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
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exec_output += PredOpExecute.subst(msrSpsrRegIop)
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msrCpsrImmCode = '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
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{ "code": msrCpsrImmCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrImmDeclare.subst(msrCpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
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exec_output += PredOpExecute.subst(msrCpsrImmIop)
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msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
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msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
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{ "code": msrSpsrImmCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrImmDeclare.subst(msrSpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
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exec_output += PredOpExecute.subst(msrSpsrImmIop)
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}};
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