2004-01-22 02:14:10 +01:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-01-22 02:14:10 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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* Miguel Serrano
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2004-01-22 02:14:10 +01:00
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*/
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2005-06-05 05:56:53 +02:00
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/** @file
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* Tsunami I/O Space mapping including RTC/timer interrupts
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2004-01-22 02:14:10 +01:00
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*/
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2005-02-21 23:32:57 +01:00
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#ifndef __DEV_TSUNAMI_IO_HH__
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#define __DEV_TSUNAMI_IO_HH__
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2004-01-22 02:14:10 +01:00
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2004-06-10 19:30:58 +02:00
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#include "base/range.hh"
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2006-11-07 01:45:00 +01:00
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#include "dev/alpha/tsunami.hh"
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2008-06-12 06:54:48 +02:00
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#include "dev/intel_8254_timer.hh"
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2008-03-25 07:15:06 +01:00
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#include "dev/mc146818.hh"
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2007-07-24 06:51:38 +02:00
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#include "dev/io_device.hh"
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#include "params/TsunamiIO.hh"
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2004-06-27 03:26:28 +02:00
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#include "sim/eventq.hh"
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2004-01-22 02:14:10 +01:00
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2005-06-05 05:56:53 +02:00
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/**
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2004-05-30 23:45:46 +02:00
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* Tsunami I/O device is a catch all for all the south bridge stuff we care
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* to implement.
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2004-01-22 02:14:10 +01:00
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*/
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2006-04-11 19:42:47 +02:00
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class TsunamiIO : public BasicPioDevice
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2004-01-22 02:14:10 +01:00
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{
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2004-01-26 19:26:34 +01:00
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private:
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struct tm tm;
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2004-01-22 02:14:10 +01:00
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protected:
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2004-01-23 01:02:07 +01:00
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2008-10-09 13:58:24 +02:00
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class RTC : public MC146818
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2008-03-25 07:15:06 +01:00
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{
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2004-02-06 00:23:16 +01:00
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public:
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2008-10-09 13:58:24 +02:00
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Tsunami *tsunami;
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RTC(const std::string &n, const TsunamiIOParams *p);
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2004-01-23 01:02:07 +01:00
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2008-03-25 07:15:06 +01:00
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protected:
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void handleEvent()
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{
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//Actually interrupt the processor here
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tsunami->cchip->postRTC();
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}
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2005-08-15 22:59:58 +02:00
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};
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2004-01-23 01:02:07 +01:00
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2004-05-30 23:45:46 +02:00
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/** Mask of the PIC1 */
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2004-02-06 00:23:16 +01:00
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uint8_t mask1;
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2004-05-30 23:45:46 +02:00
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/** Mask of the PIC2 */
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2004-02-06 00:23:16 +01:00
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uint8_t mask2;
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2004-05-30 23:45:46 +02:00
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/** Mode of PIC1. Not used for anything */
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2004-02-06 00:23:16 +01:00
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uint8_t mode1;
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2004-05-30 23:45:46 +02:00
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/** Mode of PIC2. Not used for anything */
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2004-02-06 00:23:16 +01:00
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uint8_t mode2;
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2004-01-22 06:08:48 +01:00
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2004-05-30 23:45:46 +02:00
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/** Raw PIC interrupt register before masking */
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uint8_t picr; //Raw PIC interrput register
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/** Is the pic interrupting right now or not. */
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2004-01-29 01:18:29 +01:00
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bool picInterrupting;
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2004-05-30 23:45:46 +02:00
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/** A pointer to the Tsunami device which be belong to */
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2004-01-28 03:36:46 +01:00
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Tsunami *tsunami;
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2005-08-15 22:59:58 +02:00
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/** Intel 8253 Periodic Interval Timer */
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2008-06-12 06:54:48 +02:00
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Intel8254Timer pitimer;
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2004-01-23 01:02:07 +01:00
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2008-10-09 13:58:24 +02:00
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RTC rtc;
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2008-03-25 07:15:06 +01:00
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uint8_t rtcAddr;
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2004-01-26 19:26:34 +01:00
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2004-05-30 23:45:46 +02:00
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/** The interval is set via two writes to the PIT.
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* This variable contains a flag as to how many writes have happened, and
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* the time so far.
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*/
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2005-08-15 22:59:58 +02:00
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uint16_t timerData;
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2004-01-23 01:02:07 +01:00
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2004-01-22 02:14:10 +01:00
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public:
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2004-06-01 23:36:38 +02:00
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/**
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* Return the freqency of the RTC
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* @return interrupt rate of the RTC
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*/
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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Tick frequency() const;
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2004-01-28 03:36:46 +01:00
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2006-04-10 20:14:06 +02:00
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public:
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2007-07-24 06:51:38 +02:00
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typedef TsunamiIOParams Params;
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2004-05-30 23:45:46 +02:00
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/**
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* Initialize all the data for devices supported by Tsunami I/O.
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2006-04-10 20:14:06 +02:00
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* @param p pointer to Params struct
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2004-05-30 23:45:46 +02:00
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*/
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2007-07-24 06:51:38 +02:00
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TsunamiIO(const Params *p);
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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2004-01-22 02:14:10 +01:00
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2006-10-20 09:10:12 +02:00
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virtual Tick read(PacketPtr pkt);
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virtual Tick write(PacketPtr pkt);
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2004-01-22 02:14:10 +01:00
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2004-05-30 23:45:46 +02:00
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/**
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* Post an PIC interrupt to the CPU via the CChip
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* @param bitvector interrupt to post.
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*/
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2004-01-29 01:18:29 +01:00
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void postPIC(uint8_t bitvector);
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2004-05-30 23:45:46 +02:00
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/**
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* Clear a posted interrupt
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* @param bitvector interrupt to clear
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*/
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2004-01-29 01:18:29 +01:00
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void clearPIC(uint8_t bitvector);
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2004-05-30 23:45:46 +02:00
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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2004-01-22 02:14:10 +01:00
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virtual void serialize(std::ostream &os);
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2004-05-30 23:45:46 +02:00
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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2004-01-22 02:14:10 +01:00
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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2004-06-10 19:30:58 +02:00
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2004-01-22 02:14:10 +01:00
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};
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2005-02-21 23:32:57 +01:00
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#endif // __DEV_TSUNAMI_IO_HH__
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