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load/store instruction format ... now generates load/store code and breaks it into a separate EA and MemAccess templated from how the Alpha ARch. was coded to do the same thing. arch/mips/isa/bitfields.isa: comment change arch/mips/isa/decoder.isa: re-structuring of load/store instruction definitions arch/mips/isa/formats/mem.isa: Define LoadMemory & Store Memory formats Use style of formatting & base class similar to what was used for ALPHA arch/mips/isa/formats/util.isa: Insert LoadStoreBase function here from alpha/arch/isa/mem.isa arch/mips/isa/operands.isa: change shw->sh and uhw->uh --HG-- extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
2006-02-20 20:30:23 +01:00
// -*- mode:c++ -*-
Adding the sparc ISA files which were worked on locally arch/sparc/isa_desc/bitfields.h: This file defines the bit fields used by the isa description system arch/sparc/isa_desc/decoder.h: This file describes the decoder for the isa description system arch/sparc/isa_desc/formats.h: This file declares the instruction formats arch/sparc/isa_desc/formats/basic.format: This file implements the "basic" instruction format arch/sparc/isa_desc/formats/branch.format: This file implements the "branch" instruction format arch/sparc/isa_desc/formats/integerop.format: This file implements the "integerop" instruction format arch/sparc/isa_desc/formats/mem.format: This file implements the "mem" instruction format arch/sparc/isa_desc/formats/noop.format: This file implements the "noop" instruction format arch/sparc/isa_desc/formats/trap.format: This file implements the "trap" instruction format arch/sparc/isa_desc/includes.h: This file is all of the inclues that are used by the isa description system --HG-- extra : convert_revision : 12a2ffe949317b8b57d83263a4261131b9432c2a
2006-01-10 20:57:37 +01:00
////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//
MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!! arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-22 09:33:35 +01:00
def bitfield OPCODE <31:26>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
def bitfield OPCODE_HI <31:29>;
def bitfield OPCODE_LO <28:26>;
MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!! arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-22 09:33:35 +01:00
def bitfield REGIMM <20:16>;
def bitfield REGIMM_HI <20:19>;
def bitfield REGIMM_LO <18:16>;
def bitfield FUNCTION < 5: 0>;
more changes to the decoder ... Now does special 3 table arch/mips/isa_desc/bitfields.h: Change from table names to actual bitfield name ... --HG-- extra : convert_revision : ead69065eb9c3e9c4ea4f67587a6fb07091898ed
2006-01-25 23:36:38 +01:00
def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
mainly added minor support for the basic arithmetic operations (add, mult, shift) arch/mips/isa/bitfields.def: Add comment, move definition up in file arch/mips/isa/decoder.def: add basic arithmetic operations arch/mips/isa/formats/fp.format: change Integer -> FP words arch/mips/isa/formats/int.format: Add derived IntImm class arch/mips/isa/operands.def: change to MIPS sytle operands --HG-- rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
2006-02-04 05:04:06 +01:00
// Integer operate format
more changes to the decoder ... Now does special 3 table arch/mips/isa_desc/bitfields.h: Change from table names to actual bitfield name ... --HG-- extra : convert_revision : ead69065eb9c3e9c4ea4f67587a6fb07091898ed
2006-01-25 23:36:38 +01:00
def bitfield RT <20:16>;
def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
more changes to the decoder ... Now does special 3 table arch/mips/isa_desc/bitfields.h: Change from table names to actual bitfield name ... --HG-- extra : convert_revision : ead69065eb9c3e9c4ea4f67587a6fb07091898ed
2006-01-25 23:36:38 +01:00
def bitfield RS <25:21>;
make MIPS MT instructions decodable ... arch/mips/isa/bitfields.isa: extra bitfield for decoding --HG-- extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866
2006-02-14 08:03:14 +01:00
def bitfield RS_MSB <25:25>;
more changes to the decoder ... Now does special 3 table arch/mips/isa_desc/bitfields.h: Change from table names to actual bitfield name ... --HG-- extra : convert_revision : ead69065eb9c3e9c4ea4f67587a6fb07091898ed
2006-01-25 23:36:38 +01:00
def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>;
Finally MIPS does hello world! arch/mips/isa/bitfields.isa: add RS_SRL bitfield ...these must be set to 0 for a SRL instruction arch/mips/isa/decoder.isa: Make unimplemented instructions Fail instead of just Warn Edits to SRA & SRAV instructions Implement CFC1 instructions Unaligned Memory Access Support (Maybe Not fully functional yet) Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions) arch/mips/isa/formats/branch.isa: Fix disassembly arch/mips/isa/formats/int.isa: Add sign extend Immediate and zero extend Immediate to Int class. Probably a bit unnecessary in the long run since these manipulations could be done in the actually instruction instead of keep a int value arch/mips/isa/formats/mem.isa: Comment/Remove out split-memory access code... revisit this after SimpleCPU works arch/mips/isa/formats/unimp.isa: Add inst2string function to Unimplemented panic. PRints out the instruction binary to help in debuggin arch/mips/isa/formats/unknown.isa: define inst2string function , use in unknown disassembly and panic function arch/mips/isa/operands.isa: Make "Mem" default to a unsigned word since this is MIPS32 arch/mips/isa_traits.hh: change return values to 32 instead of 64 arch/mips/linux_process.cc: assign some syscalls to the right functions cpu/static_inst.hh: more debug functions for MIPS (these will be move to the mips directory soon) mem/page_table.cc: mem/page_table.hh: toward a better implementation for unaligned memory access mem/request.hh: NO ALIGN FAULT flag added to support unaligned memory access sim/syscall_emul.cc: additional SyscallVerbose comments --HG-- extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c
2006-04-10 18:23:17 +02:00
def bitfield RS_SRL <25:22>;
more changes to the decoder ... Now does special 3 table arch/mips/isa_desc/bitfields.h: Change from table names to actual bitfield name ... --HG-- extra : convert_revision : ead69065eb9c3e9c4ea4f67587a6fb07091898ed
2006-01-25 23:36:38 +01:00
bitfields definition to support current decoder.h --HG-- extra : convert_revision : 75ccc53181b857605d051024d86ef62ec43f3b7f
2006-01-26 23:07:01 +01:00
def bitfield RD <15:11>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
mainly added minor support for the basic arithmetic operations (add, mult, shift) arch/mips/isa/bitfields.def: Add comment, move definition up in file arch/mips/isa/decoder.def: add basic arithmetic operations arch/mips/isa/formats/fp.format: change Integer -> FP words arch/mips/isa/formats/int.format: Add derived IntImm class arch/mips/isa/operands.def: change to MIPS sytle operands --HG-- rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
2006-02-04 05:04:06 +01:00
def bitfield INTIMM <15: 0>; // integer immediate (literal)
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
// Floating-point operate format
mainly added minor support for the basic arithmetic operations (add, mult, shift) arch/mips/isa/bitfields.def: Add comment, move definition up in file arch/mips/isa/decoder.def: add basic arithmetic operations arch/mips/isa/formats/fp.format: change Integer -> FP words arch/mips/isa/formats/int.format: Add derived IntImm class arch/mips/isa/operands.def: change to MIPS sytle operands --HG-- rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
2006-02-04 05:04:06 +01:00
def bitfield FMT <25:21>;
updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
2006-03-08 08:05:38 +01:00
def bitfield FR <25:21>;
bitfields definition to support current decoder.h --HG-- extra : convert_revision : 75ccc53181b857605d051024d86ef62ec43f3b7f
2006-01-26 23:07:01 +01:00
def bitfield FT <20:16>;
def bitfield FS <15:11>;
def bitfield FD <10:6>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!! arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-22 09:33:35 +01:00
def bitfield ND <17:17>;
def bitfield TF <16:16>;
bitfields definition to support current decoder.h --HG-- extra : convert_revision : 75ccc53181b857605d051024d86ef62ec43f3b7f
2006-01-26 23:07:01 +01:00
def bitfield MOVCI <16:16>;
def bitfield MOVCF <16:16>;
def bitfield SRL <21:21>;
def bitfield SRLV < 6: 6>;
def bitfield SA <10: 6>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
Start working on more complex FP tests Debug FP instructions to handle these FP insts arch/mips/isa/bitfields.isa: add Bitfield for Floating Point Condition Codes arch/mips/isa/decoder.isa: Follow instruction naming style with FP single insts Send the float value to the convert&round functions in single FP add ll inst support add 'token' sc support arch/mips/isa_traits.cc: Add SINGLE->WORD, WORD->SINGLE, & WORD->DOUBLE conversions arch/mips/regfile.hh: update header files arch/mips/regfile/float_regfile.hh: Add more FP registers --HG-- rename : arch/mips/int_regfile.hh => arch/mips/regfile/int_regfile.hh rename : arch/mips/misc_regfile.hh => arch/mips/regfile/misc_regfile.hh extra : convert_revision : 92faf0bfd8542ade762ac569ec158d198f6a9c7e
2006-05-08 09:59:40 +02:00
// Floating Point Condition Codes
def bitfield CC <10:8>;
def bitfield BRANCH_CC <20:18>;
updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
2006-03-08 08:05:38 +01:00
// CP0 Register Select
def bitfield SEL < 2: 0>;
bitfields definition to support current decoder.h --HG-- extra : convert_revision : 75ccc53181b857605d051024d86ef62ec43f3b7f
2006-01-26 23:07:01 +01:00
// Interrupts
def bitfield SC < 5: 5>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
bitfields definition to support current decoder.h --HG-- extra : convert_revision : 75ccc53181b857605d051024d86ef62ec43f3b7f
2006-01-26 23:07:01 +01:00
// Branch format
def bitfield OFFSET <15: 0>; // displacement
load/store instruction format ... now generates load/store code and breaks it into a separate EA and MemAccess templated from how the Alpha ARch. was coded to do the same thing. arch/mips/isa/bitfields.isa: comment change arch/mips/isa/decoder.isa: re-structuring of load/store instruction definitions arch/mips/isa/formats/mem.isa: Define LoadMemory & Store Memory formats Use style of formatting & base class similar to what was used for ALPHA arch/mips/isa/formats/util.isa: Insert LoadStoreBase function here from alpha/arch/isa/mem.isa arch/mips/isa/operands.isa: change shw->sh and uhw->uh --HG-- extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
2006-02-20 20:30:23 +01:00
// Jmp format
name changes ... minor IntOP format change arch/mips/isa/formats/int.format: Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from their reg-reg counterparts --HG-- rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
2006-02-08 00:36:08 +01:00
def bitfield JMPTARG <25: 0>;
MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!! arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-22 09:33:35 +01:00
def bitfield HINT <10: 6>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
name changes ... minor IntOP format change arch/mips/isa/formats/int.format: Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from their reg-reg counterparts --HG-- rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
2006-02-08 00:36:08 +01:00
def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE <15:13>;
first version of my decoder function skeleton - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) arch/mips/isa_desc/bitfields.h: initial bitfield constants ... copied some from original alpha bitfields arch/mips/isa_desc/decoder.h: decoder function skeleton pt.1 - this will decode the instructions but not doing anything to create the C++ object yet (the 1st of many steps!) --HG-- extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 23:06:23 +01:00
// M5 instructions
def bitfield M5FUNC <7:0>;
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