2011-02-23 22:35:25 +01:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2011-07-10 19:56:09 +02:00
|
|
|
sim_seconds 0.274500 # Number of seconds simulated
|
|
|
|
|
sim_ticks 274500333500 # Number of ticks simulated
|
2011-02-23 22:35:25 +01:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2011-07-10 19:56:09 +02:00
|
|
|
host_inst_rate 56944 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_tick_rate 25971361 # Simulator tick rate (ticks/s)
|
|
|
|
|
host_mem_usage 245756 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 10569.35 # Real time elapsed on the host
|
2011-02-23 22:35:25 +01:00
|
|
|
sim_insts 601856964 # Number of instructions simulated
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.read_hits 114517568 # DTB read hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.read_misses 2631 # DTB read misses
|
|
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.read_accesses 114520199 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_hits 39666597 # DTB write hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.write_misses 2302 # DTB write misses
|
|
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.write_accesses 39668899 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 154184165 # DTB hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.data_misses 4933 # DTB misses
|
|
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.data_accesses 154189098 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 27986226 # ITB hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.itb.fetch_misses 22 # ITB misses
|
|
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.itb.fetch_accesses 27986248 # ITB accesses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.numCycles 549000668 # number of cpu cycles simulated
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed
|
|
|
|
|
system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed.
|
|
|
|
|
system.cpu.activity 89.164571 # Percentage of cycles cpu is active
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
|
|
|
|
system.cpu.comStores 39451321 # Number of Store instructions committed
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
|
|
|
|
system.cpu.comNops 36304520 # Number of Nop instructions committed
|
|
|
|
|
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
|
|
|
|
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
|
|
|
|
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread)
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread)
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread)
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups
|
|
|
|
|
system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups
|
|
|
|
|
system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True).
|
|
|
|
|
system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False).
|
|
|
|
|
system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
|
|
|
|
|
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
|
|
|
|
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic
|
|
|
|
|
system.cpu.agen_unit.agens 154582342 # Number of Address Generations
|
|
|
|
|
system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken.
|
|
|
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
|
|
|
system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted
|
|
|
|
|
system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted
|
|
|
|
|
system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts
|
|
|
|
|
system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
|
|
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts).
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.replacements 30 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 27985205 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1019 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 451299 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 152394244 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1571119 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.writebacks 408188 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.replacements 73797 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 364156 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 92094 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses)
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 59345 # number of writebacks
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-23 22:35:25 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
