sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt

1586 lines
184 KiB
Plaintext
Raw Normal View History

arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 47.216814 # Number of seconds simulated
sim_ticks 47216814145000 # Number of ticks simulated
final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for clean eviction addition
2015-07-30 09:42:27 +02:00
host_inst_rate 1175010 # Simulator instruction rate (inst/s)
host_op_rate 1382295 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56876129335 # Simulator tick rate (ticks/s)
host_mem_usage 728240 # Number of bytes of host memory used
host_seconds 830.17 # Real time elapsed on the host
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_insts 975457230 # Number of instructions simulated
sim_ops 1147538415 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 152256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 127104 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3638260 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 62923528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 221632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 219968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2412168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 46368688 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 419904 # Number of bytes read from this memory
system.physmem.bytes_read::total 116483508 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3638260 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2412168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6050428 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 101038848 # Number of bytes written to this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_written::total 101059432 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2379 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1986 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 97255 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 983193 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3463 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 3437 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 37797 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 724527 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6561 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1860598 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1578732 # Number of write requests responded to by this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_writes::total 1581306 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3225 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2692 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 77054 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1332651 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 4694 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 4659 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 51087 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 982038 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8893 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2466992 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 77054 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 51087 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 128141 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2139891 # Write bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_write::total 2140327 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2139891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3225 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2692 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 77054 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1333087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 4694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 4659 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 51087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 982038 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8893 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4607319 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.read_hits 92662773 # DTB read hits
system.cpu0.dtb.read_misses 88786 # DTB read misses
system.cpu0.dtb.write_hits 85694958 # DTB write hits
system.cpu0.dtb.write_misses 36443 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.hits 178357731 # DTB hits
system.cpu0.dtb.misses 125229 # DTB misses
system.cpu0.dtb.accesses 178482960 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walks 61377 # Table walker walks requested
system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 497696393 # ITB inst hits
system.cpu0.itb.inst_misses 61377 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
system.cpu0.itb.hits 497696393 # DTB hits
system.cpu0.itb.misses 61377 # DTB misses
system.cpu0.itb.accesses 497757770 # DTB accesses
system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.committedInsts 497466384 # Number of instructions committed
system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
system.cpu0.num_int_insts 536103359 # number of integer instructions
system.cpu0.num_fp_insts 526132 # number of float instructions
system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
system.cpu0.num_mem_refs 178459396 # number of memory refs
system.cpu0.num_load_insts 92737001 # Number of load instructions
system.cpu0.num_store_insts 85722395 # Number of store instructions
system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
system.cpu0.Branches 111287587 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction
system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction
system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.op_class::total 585300003 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.tags.replacements 6272773 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 80919787 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 80919787 # number of WriteReq hits
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262007 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 262007 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036572 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 2036572 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 167134698 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 167134698 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 167350352 # number of overall hits
system.cpu0.dcache.overall_hits::total 167350352 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1475655 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1475655 # number of WriteReq misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831713 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 831713 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158571 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 158571 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 4785037 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 4785037 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 5557176 # number of overall misses
system.cpu0.dcache.overall_misses::total 5557176 # number of overall misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760444 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760444 # miss rate for WriteLineReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032140 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.032140 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.writebacks::writebacks 4472506 # number of writebacks
system.cpu0.dcache.writebacks::total 4472506 # number of writebacks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.replacements 5539081 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits
system.cpu0.icache.overall_hits::total 492212891 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses
system.cpu0.icache.overall_misses::total 5539598 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.tags.replacements 2713035 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16212.776574 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 18780735 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2729020 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.881861 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 5698.548759 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.293580 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 53.073220 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4549.413482 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5859.447533 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.347812 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003192 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003239 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.277674 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357632 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.989549 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1169 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4652 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5280 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4600 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 396071662 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 396071662 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267140 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140047 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 407187 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 4472506 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 4472506 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3480 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 3480 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634900 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 634900 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4970860 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 4970860 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2942102 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2942102 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223126 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 223126 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267140 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140047 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 4970860 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3577002 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 8955049 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267140 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140047 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 4970860 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3577002 # number of overall hits
system.cpu0.l2cache.overall_hits::total 8955049 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11279 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8435 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 19714 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128321 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 128321 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158571 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 158571 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709333 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 709333 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568738 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 568738 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1259235 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1259235 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608208 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 608208 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11279 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8435 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 568738 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1968568 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2557020 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11279 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8435 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 568738 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1968568 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2557020 # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278419 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148482 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 426901 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 4472506 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 4472506 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131801 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 131801 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158571 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 158571 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344233 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1344233 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831334 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 831334 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278419 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148482 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.demand_accesses::total 11512069 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278419 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148482 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.overall_accesses::total 11512069 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056808 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.046179 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973597 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973597 # miss rate for UpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527686 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527686 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102668 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102668 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299722 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299722 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731605 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731605 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056808 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102668 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354980 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.222116 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056808 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102668 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354980 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.222116 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.writebacks::writebacks 1573891 # number of writebacks
system.cpu0.l2cache.writebacks::total 1573891 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.trans_dist::Writeback 4472506 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 7339348 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 131801 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158571 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 290372 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1344233 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1344233 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 831334 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 831334 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16704527 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19737201 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.pkt_count::total 37536458 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641350217 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.pkt_size::total 1000435909 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 3360861 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 27849165 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 1.133662 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.340289 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::1 24126791 86.63% 86.63% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 3722374 13.37% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 27849165 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.read_hits 90153061 # DTB read hits
system.cpu1.dtb.read_misses 111753 # DTB read misses
system.cpu1.dtb.write_hits 81132787 # DTB write hits
system.cpu1.dtb.write_misses 32288 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.hits 171285848 # DTB hits
system.cpu1.dtb.misses 144041 # DTB misses
system.cpu1.dtb.accesses 171429889 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walks 60885 # Table walker walks requested
system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 478248118 # ITB inst hits
system.cpu1.itb.inst_misses 60885 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
system.cpu1.itb.hits 478248118 # DTB hits
system.cpu1.itb.misses 60885 # DTB misses
system.cpu1.itb.accesses 478309003 # DTB accesses
system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.committedInsts 477990846 # Number of instructions committed
system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
system.cpu1.num_int_insts 516282159 # number of integer instructions
system.cpu1.num_fp_insts 374678 # number of float instructions
system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
system.cpu1.num_mem_refs 171406825 # number of memory refs
system.cpu1.num_load_insts 90251973 # Number of load instructions
system.cpu1.num_store_insts 81154852 # Number of store instructions
system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
system.cpu1.Branches 106497601 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.op_class::total 562879339 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements 5945049 # number of replacements
system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteReq_hits::cpu1.data 76990238 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 76990238 # number of WriteReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048840 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 2048840 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 160687802 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 160687802 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 160875656 # number of overall hits
system.cpu1.dcache.overall_hits::total 160875656 # number of overall hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteReq_misses::cpu1.data 1453238 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1453238 # number of WriteReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158909 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 158909 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 4811460 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 4811460 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 5603811 # number of overall misses
system.cpu1.dcache.overall_misses::total 5603811 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018526 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.018526 # miss rate for WriteReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071978 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071978 # miss rate for StoreCondReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.writebacks::writebacks 4032489 # number of writebacks
system.cpu1.dcache.writebacks::total 4032489 # number of writebacks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.icache.tags.replacements 4741297 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits
system.cpu1.icache.overall_hits::total 473560604 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses
system.cpu1.icache.overall_misses::total 4741809 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.tags.replacements 2278625 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13455.366056 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 17413486 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2294680 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 7.588634 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 5192.867159 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.806245 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 99.441300 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2834.629918 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5261.621433 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.316947 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004078 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006069 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173012 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.321144 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.821250 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1614 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5923 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3815 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 360485676 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 360485676 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324846 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140054 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 464900 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 4032489 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 4032489 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3822 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 3822 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614016 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 614016 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4217303 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4217303 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057649 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 3057649 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161208 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 161208 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324846 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140054 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4217303 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3671665 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 8353868 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324846 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140054 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4217303 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3671665 # number of overall hits
system.cpu1.l2cache.overall_hits::total 8353868 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12306 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9777 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 22083 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133739 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 133739 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158909 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 158909 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701874 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 701874 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 524506 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 524506 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239744 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 1239744 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265638 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 265638 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12306 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9777 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 524506 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1941618 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 2488207 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12306 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9777 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 524506 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1941618 # number of overall misses
system.cpu1.l2cache.overall_misses::total 2488207 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337152 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149831 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 486983 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 4032489 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 4032489 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137561 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 137561 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158909 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 158909 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337152 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149831 # number of demand (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.demand_accesses::total 10842075 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337152 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149831 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.overall_accesses::total 10842075 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065254 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.045347 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972216 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972216 # miss rate for UpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533383 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533383 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110613 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110613 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288487 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288487 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622327 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622327 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065254 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110613 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345897 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.229495 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065254 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110613 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345897 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.229495 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.writebacks::writebacks 1184748 # number of writebacks
system.cpu1.l2cache.writebacks::total 1184748 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.trans_dist::Writeback 4032489 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 6653857 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 137561 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158909 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 296470 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225175 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643731 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.pkt_count::total 34068350 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617367804 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.pkt_size::total 925641876 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 3842126 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 26053175 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 1.164109 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.370374 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::1 21777626 83.59% 83.59% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 4275549 16.41% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 26053175 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136634 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements 115585 # number of replacements
system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
system.iocache.tags.data_accesses 1040793 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.overall_misses::realview.ide 8876 # number of overall misses
system.iocache.overall_misses::total 8916 # number of overall misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.replacements 1751385 # number of replacements
system.l2c.tags.tagsinuse 62313.380560 # Cycle average of tags in use
system.l2c.tags.total_refs 6017106 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1809468 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 3.325345 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 34286.931814 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.043983 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 59.106418 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3327.548165 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6997.138223 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.986034 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 428.835942 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3021.438473 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 13835.351509 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.523177 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000718 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000902 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.050774 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.106768 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004730 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.006544 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.046103 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.211111 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.950827 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 57863 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 545 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3434 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 48241 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.882919 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 85814440 # Number of tag accesses
system.l2c.tags.data_accesses 85814440 # Number of data accesses
system.l2c.Writeback_hits::writebacks 2758639 # number of Writeback hits
system.l2c.Writeback_hits::total 2758639 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 13259 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 10916 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 24175 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 1481 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 1240 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 2721 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 318588 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 264415 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 583003 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6289 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4561 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 514584 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 748348 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5382 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3638 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 486810 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 695012 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2464624 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6289 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4561 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 514584 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 1066936 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5382 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3638 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 486810 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 959427 # number of demand (read+write) hits
system.l2c.demand_hits::total 3047627 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6289 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4561 # number of overall hits
system.l2c.overall_hits::cpu0.inst 514584 # number of overall hits
system.l2c.overall_hits::cpu0.data 1066936 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5382 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3638 # number of overall hits
system.l2c.overall_hits::cpu1.inst 486810 # number of overall hits
system.l2c.overall_hits::cpu1.data 959427 # number of overall hits
system.l2c.overall_hits::total 3047627 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 58599 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 54084 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 112683 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 7811 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 7438 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 15249 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 816245 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 547345 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 1363590 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2379 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1986 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 54154 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 180703 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3463 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3437 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 37696 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 186059 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 469877 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2379 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1986 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 54154 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 996948 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3463 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 3437 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 37696 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 733404 # number of demand (read+write) misses
system.l2c.demand_misses::total 1833467 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2379 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1986 # number of overall misses
system.l2c.overall_misses::cpu0.inst 54154 # number of overall misses
system.l2c.overall_misses::cpu0.data 996948 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3463 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 3437 # number of overall misses
system.l2c.overall_misses::cpu1.inst 37696 # number of overall misses
system.l2c.overall_misses::cpu1.data 733404 # number of overall misses
system.l2c.overall_misses::total 1833467 # number of overall misses
system.l2c.Writeback_accesses::writebacks 2758639 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 2758639 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 71858 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 65000 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 136858 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 9292 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 8678 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 17970 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 1134833 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 811760 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 1946593 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6547 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 568738 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 929051 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8845 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7075 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 524506 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 881071 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 2934501 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6547 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 568738 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 2063884 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 8845 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7075 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 524506 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 1692831 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 4881094 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6547 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 568738 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 2063884 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 8845 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7075 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 524506 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 1692831 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 4881094 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815483 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.832062 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.823357 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.840616 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.857110 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.848581 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.719264 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.674269 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.700501 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303345 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095218 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194503 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485795 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.071870 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211174 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.160122 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.303345 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.095218 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.483045 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.485795 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.071870 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.433241 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.375626 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.303345 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.095218 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.483045 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.485795 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.071870 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.433241 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.375626 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.writebacks::writebacks 1472038 # number of writebacks
system.l2c.writebacks::total 1472038 # number of writebacks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 82131 # Transaction distribution
system.membus.trans_dist::ReadResp 560921 # Transaction distribution
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.trans_dist::WriteReq 38802 # Transaction distribution
system.membus.trans_dist::WriteResp 38802 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::Writeback 1578732 # Transaction distribution
stats: Update stats for clean eviction addition
2015-07-30 09:42:27 +02:00
system.membus.trans_dist::CleanEvict 418759 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::UpgradeReq 328366 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 314759 # Transaction distribution
system.membus.trans_dist::UpgradeResp 149960 # Transaction distribution
system.membus.trans_dist::ReadExReq 1611572 # Transaction distribution
system.membus.trans_dist::ReadExResp 1341565 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 478790 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes)
stats: Update stats for clean eviction addition
2015-07-30 09:42:27 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6659522 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 6809742 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346873 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 346873 # Packet count per connected master and slave (bytes)
stats: Update stats for clean eviction addition
2015-07-30 09:42:27 +02:00
system.membus.pkt_count::total 7156615 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210336476 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 210547473 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 217946321 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update stats for clean eviction addition
2015-07-30 09:42:27 +02:00
system.membus.snoop_fanout::samples 4958639 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for clean eviction addition
2015-07-30 09:42:27 +02:00
system.membus.snoop_fanout::1 4958639 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats for clean eviction addition
2015-07-30 09:42:27 +02:00
system.membus.snoop_fanout::total 4958639 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 3716153 # Transaction distribution
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::Writeback 2758639 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2438361 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 330513 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 317480 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 647993 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2216600 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2216600 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 3634020 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9937165 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8498931 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 18436096 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301383709 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 250013636 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 551397345 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 117333 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 11932192 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.009692 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.097969 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.snoop_fanout::1 11816548 99.03% 99.03% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 115644 0.97% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.snoop_fanout::total 11932192 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink