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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
arm, stats: Update stats to reflect changes to generic timer The addition of a virtual timer affects stats in minor and o3.
2015-05-23 14:50:57 +02:00
gem5 compiled May 6 2015 17:58:20
gem5 started May 6 2015 20:51:07
gem5 executing on e104799-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
Global frequency set at 1000000000000 ticks per second
arm, stats: Update stats to reflect changes to generic timer The addition of a virtual timer affects stats in minor and o3.
2015-05-23 14:50:57 +02:00
0: system.cpu0.isa: ISA system set to: 0x4a64c00 0x4a64c00
0: system.cpu1.isa: ISA system set to: 0x4a64c00 0x4a64c00
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