sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

arm, stats: Update stats to reflect changes to generic timer

Browse source 
The addition of a virtual timer affects stats in minor and o3.
This commit is contained in:
Andreas Sandberg 2015-05-23 13:50:57 +01:00
parent f3f06e1684
commit dbdb9ab518
12 changed files with 3407 additions and 3476 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
View file

@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_loader=/work/gem5/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=469827632
gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@ -44,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/z/stever/hg/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -87,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@ -165,7 +163,7 @@ dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
type=BranchPredictor
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
@ -179,7 +177,6 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu0.dcache]
type=BaseCache
@ -202,7 +199,6 @@ size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=16
cpu_side=system.cpu0.dcache_port
mem_side=system.cpu0.toL2Bus.slave[1]
@ -649,7 +645,7 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
@ -662,7 +658,6 @@ size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.cpu0.toL2Bus.slave[0]
@ -773,7 +768,6 @@ size=1048576
system=system
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[0]
@ -899,7 +893,7 @@ dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
type=BranchPredictor
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
@ -913,7 +907,6 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu1.dcache]
type=BaseCache
@ -936,7 +929,6 @@ size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=16
cpu_side=system.cpu1.dcache_port
mem_side=system.cpu1.toL2Bus.slave[1]
@ -1383,7 +1375,7 @@ assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
forward_snoops=false
hit_latency=1
is_top_level=true
max_miss_count=0
@ -1396,7 +1388,6 @@ size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.cpu1.toL2Bus.slave[0]
@ -1507,7 +1498,6 @@ size=1048576
system=system
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[1]
@ -1621,7 +1611,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[3]
@ -1657,7 +1646,6 @@ size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -1686,7 +1674,7 @@ system=system
use_default_range=false
width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
@ -2025,7 +2013,8 @@ pio=system.iobus.master[25]
type=GenericTimer
eventq_index=0
gic=system.realview.gic
int_num=29
int_phys=29
int_virt=27
system=system
[system.realview.gic]
@ -2038,7 +2027,6 @@ dist_pio_delay=10000
eventq_index=0
int_latency=10000
it_lines=128
msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
@ -2056,6 +2044,7 @@ pio_latency=10000
pixel_clock=7299
system=system
vnc=system.vncserver
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
@ -2225,7 +2214,7 @@ int_num_watchdog=30
pio_addr=738721792
pio_latency=100000
system=system
pio=system.membus.master[3]
pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
@ -2407,7 +2396,7 @@ platform=system.realview
ppint=25
system=system
vcpu_addr=738222080
pio=system.membus.master[4]
pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory

20
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
View file

@ -1,19 +1,19 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
gem5 compiled May 6 2015 17:58:20
gem5 started May 6 2015 20:43:49
gem5 executing on e104799-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu0.isa: ISA system set to: 0x36c6a30 0x36c6a30
0: system.cpu1.isa: ISA system set to: 0x36c6a30 0x36c6a30
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu0.isa: ISA system set to: 0x50ed000 0x50ed000
0: system.cpu1.isa: ISA system set to: 0x50ed000 0x50ed000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2846097440000 because m5_exit instruction encountered
Exiting @ tick 2846106511000 because m5_exit instruction encountered

4592
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

30
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
View file

@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_loader=/work/gem5/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=469827632
gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@ -44,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/z/stever/hg/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -87,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@ -165,7 +163,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
@ -179,7 +177,6 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
@ -202,7 +199,6 @@ size=32768
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -662,7 +658,6 @@ size=32768
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -773,7 +768,6 @@ size=4194304
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -862,7 +856,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[3]
@ -891,7 +884,7 @@ system=system
use_default_range=false
width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
@ -1230,7 +1223,8 @@ pio=system.iobus.master[25]
type=GenericTimer
eventq_index=0
gic=system.realview.gic
int_num=29
int_phys=29
int_virt=27
system=system
[system.realview.gic]
@ -1243,7 +1237,6 @@ dist_pio_delay=10000
eventq_index=0
int_latency=10000
it_lines=128
msix_addr=0
platform=system.realview
system=system
pio=system.membus.master[2]
@ -1261,6 +1254,7 @@ pio_latency=10000
pixel_clock=7299
system=system
vnc=system.vncserver
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
@ -1430,7 +1424,7 @@ int_num_watchdog=30
pio_addr=738721792
pio_latency=100000
system=system
pio=system.membus.master[3]
pio=system.membus.master[4]
[system.realview.mmc_fake]
type=AmbaFake
@ -1612,7 +1606,7 @@ platform=system.realview
ppint=25
system=system
vcpu_addr=738222080
pio=system.membus.master[4]
pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
View file

@ -1,18 +1,18 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
gem5 compiled May 6 2015 17:58:20
gem5 started May 6 2015 19:26:45
gem5 executing on e104799-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu.isa: ISA system set to: 0x3fbcc30 0x3fbcc30
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu.isa: ISA system set to: 0x3b57000 0x3b57000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2852831758500 because m5_exit instruction encountered
Exiting @ tick 2852795541500 because m5_exit instruction encountered

1811
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
View file

File diff suppressed because it is too large Load diff

152
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_loader=/work/gem5/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=469827632
gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@ -44,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -87,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@ -223,7 +221,6 @@ size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=16
cpu_side=system.cpu0.dcache_port
mem_side=system.cpu0.toL2Bus.slave[1]
@ -295,9 +292,9 @@ opList=system.cpu0.fuPool.FUList0.opList
[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList1]
type=FUDesc
@ -309,23 +306,23 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 sys
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=IntDiv
opLat=12
pipelined=false
[system.cpu0.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IprAccess
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList2]
type=FUDesc
@ -337,9 +334,9 @@ opList=system.cpu0.fuPool.FUList2.opList
[system.cpu0.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList3]
type=FUDesc
@ -351,9 +348,9 @@ opList=system.cpu0.fuPool.FUList3.opList
[system.cpu0.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList4]
type=FUDesc
@ -365,184 +362,184 @@ opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 s
[system.cpu0.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=4
pipelined=true
[system.cpu0.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=4
pipelined=true
[system.cpu0.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=4
pipelined=true
[system.cpu0.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=4
pipelined=true
[system.cpu0.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=9
pipelined=true
[system.cpu0.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=9
pipelined=true
[system.cpu0.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList21]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
issueLat=9
opClass=FloatDiv
opLat=9
pipelined=false
[system.cpu0.fuPool.FUList4.opList24]
type=OpDesc
eventq_index=0
issueLat=33
opClass=FloatSqrt
opLat=33
pipelined=false
[system.cpu0.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu0.icache]
type=BaseCache
@ -565,7 +562,6 @@ size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.cpu0.toL2Bus.slave[0]
@ -676,7 +672,6 @@ size=1048576
system=system
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu0.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[0]
@ -860,7 +855,6 @@ size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=16
cpu_side=system.cpu1.dcache_port
mem_side=system.cpu1.toL2Bus.slave[1]
@ -932,9 +926,9 @@ opList=system.cpu1.fuPool.FUList0.opList
[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList1]
type=FUDesc
@ -946,23 +940,23 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 sys
[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=IntDiv
opLat=12
pipelined=false
[system.cpu1.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IprAccess
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList2]
type=FUDesc
@ -974,9 +968,9 @@ opList=system.cpu1.fuPool.FUList2.opList
[system.cpu1.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList3]
type=FUDesc
@ -988,9 +982,9 @@ opList=system.cpu1.fuPool.FUList3.opList
[system.cpu1.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList4]
type=FUDesc
@ -1002,184 +996,184 @@ opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 s
[system.cpu1.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=4
pipelined=true
[system.cpu1.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=4
pipelined=true
[system.cpu1.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=4
pipelined=true
[system.cpu1.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=4
pipelined=true
[system.cpu1.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=9
pipelined=true
[system.cpu1.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=9
pipelined=true
[system.cpu1.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList21]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
issueLat=9
opClass=FloatDiv
opLat=9
pipelined=false
[system.cpu1.fuPool.FUList4.opList24]
type=OpDesc
eventq_index=0
issueLat=33
opClass=FloatSqrt
opLat=33
pipelined=false
[system.cpu1.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu1.icache]
type=BaseCache
@ -1202,7 +1196,6 @@ size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.cpu1.toL2Bus.slave[0]
@ -1313,7 +1306,6 @@ size=1048576
system=system
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu1.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[1]
@ -1427,7 +1419,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[3]
@ -1463,7 +1454,6 @@ size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -1831,7 +1821,8 @@ pio=system.iobus.master[25]
type=GenericTimer
eventq_index=0
gic=system.realview.gic
int_num=29
int_phys=29
int_virt=27
system=system
[system.realview.gic]
@ -1861,6 +1852,7 @@ pio_latency=10000
pixel_clock=7299
system=system
vnc=system.vncserver
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]

19
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,20 +1,19 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Apr 22 2015 10:58:25
gem5 started Apr 22 2015 15:52:40
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
gem5 compiled May 6 2015 17:58:20
gem5 started May 6 2015 18:01:09
gem5 executing on e104799-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu0.isa: ISA system set to: 0x4163810 0x4163810
0: system.cpu1.isa: ISA system set to: 0x4163810 0x4163810
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu0.isa: ISA system set to: 0x4207000 0x4207000
0: system.cpu1.isa: ISA system set to: 0x4207000 0x4207000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@ -30,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2625395606000 because m5_exit instruction encountered
Exiting @ tick 2625378187500 because m5_exit instruction encountered

16
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.625378 # Nu
sim_ticks 2625378187500 # Number of ticks simulated
final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 94574 # Simulator instruction rate (inst/s)
host_op_rate 114754 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2065319127 # Simulator tick rate (ticks/s)
host_mem_usage 650700 # Number of bytes of host memory used
host_seconds 1271.17 # Real time elapsed on the host
host_inst_rate 105357 # Simulator instruction rate (inst/s)
host_op_rate 127837 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2300779000 # Simulator tick rate (ticks/s)
host_mem_usage 602544 # Number of bytes of host memory used
host_seconds 1141.08 # Real time elapsed on the host
sim_insts 120220550 # Number of instructions simulated
sim_ops 145872273 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -1570,8 +1570,8 @@ system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # La
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 35319893 # Number of BP lookups
system.cpu1.branchPred.condPredicted 12619406 # Number of conditional branches predicted
system.cpu1.branchPred.lookups 35319894 # Number of BP lookups
system.cpu1.branchPred.condPredicted 12619407 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits
@ -1801,7 +1801,7 @@ system.cpu1.numWorkItemsStarted 0 # nu
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 35319893 # Number of branches that fetch encountered
system.cpu1.fetch.Branches 35319894 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing

156
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
View file

@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_loader=/work/gem5/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=469827632
gic_cpu_addr=738205696
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@ -44,7 +42,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -87,7 +85,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@ -226,7 +224,6 @@ size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
@ -298,9 +295,9 @@ opList=system.cpu0.fuPool.FUList0.opList
[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList1]
type=FUDesc
@ -312,16 +309,16 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu0.fuPool.FUList2]
type=FUDesc
@ -333,23 +330,23 @@ opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 sys
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList3]
type=FUDesc
@ -361,23 +358,23 @@ opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 sys
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu0.fuPool.FUList4]
type=FUDesc
@ -389,9 +386,9 @@ opList=system.cpu0.fuPool.FUList4.opList
[system.cpu0.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5]
type=FUDesc
@ -403,142 +400,142 @@ opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 s
[system.cpu0.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList6]
type=FUDesc
@ -550,9 +547,9 @@ opList=system.cpu0.fuPool.FUList6.opList
[system.cpu0.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList7]
type=FUDesc
@ -564,16 +561,16 @@ opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
[system.cpu0.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu0.fuPool.FUList8]
type=FUDesc
@ -585,9 +582,9 @@ opList=system.cpu0.fuPool.FUList8.opList
[system.cpu0.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu0.icache]
type=BaseCache
@ -610,7 +607,6 @@ size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
@ -865,9 +861,9 @@ opList=system.cpu1.fuPool.FUList0.opList
[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList1]
type=FUDesc
@ -879,16 +875,16 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
pipelined=true
[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu1.fuPool.FUList2]
type=FUDesc
@ -900,23 +896,23 @@ opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 sys
[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList3]
type=FUDesc
@ -928,23 +924,23 @@ opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 sys
[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu1.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu1.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu1.fuPool.FUList4]
type=FUDesc
@ -956,9 +952,9 @@ opList=system.cpu1.fuPool.FUList4.opList
[system.cpu1.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5]
type=FUDesc
@ -970,142 +966,142 @@ opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 s
[system.cpu1.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList6]
type=FUDesc
@ -1117,9 +1113,9 @@ opList=system.cpu1.fuPool.FUList6.opList
[system.cpu1.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList7]
type=FUDesc
@ -1131,16 +1127,16 @@ opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
[system.cpu1.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu1.fuPool.FUList8]
type=FUDesc
@ -1152,9 +1148,9 @@ opList=system.cpu1.fuPool.FUList8.opList
[system.cpu1.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu1.isa]
type=ArmISA
@ -1285,7 +1281,6 @@ size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[3]
@ -1321,7 +1316,6 @@ size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -1689,7 +1683,8 @@ pio=system.iobus.master[25]
type=GenericTimer
eventq_index=0
gic=system.realview.gic
int_num=29
int_phys=29
int_virt=27
system=system
[system.realview.gic]
@ -1719,6 +1714,7 @@ pio_latency=10000
pixel_clock=7299
system=system
vnc=system.vncserver
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Apr 22 2015 10:58:25
gem5 started Apr 22 2015 11:13:13
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
gem5 compiled May 6 2015 17:58:20
gem5 started May 6 2015 20:51:07
gem5 executing on e104799-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
0: system.cpu0.isa: ISA system set to: 0x351fd50 0x351fd50
0: system.cpu1.isa: ISA system set to: 0x351fd50 0x351fd50
0: system.cpu0.isa: ISA system set to: 0x4a64c00 0x4a64c00
0: system.cpu1.isa: ISA system set to: 0x4a64c00 0x4a64c00

16
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.804323 # Nu
sim_ticks 2804323403500 # Number of ticks simulated
final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 111575 # Simulator instruction rate (inst/s)
host_op_rate 135423 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2674508102 # Simulator tick rate (ticks/s)
host_mem_usage 626368 # Number of bytes of host memory used
host_seconds 1048.54 # Real time elapsed on the host
host_inst_rate 111566 # Simulator instruction rate (inst/s)
host_op_rate 135412 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2674295919 # Simulator tick rate (ticks/s)
host_mem_usage 578464 # Number of bytes of host memory used
host_seconds 1048.62 # Real time elapsed on the host
sim_insts 116990114 # Number of instructions simulated
sim_ops 141995948 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -347,8 +347,8 @@ system.cf0.dma_read_txs 1 # Nu
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 26894348 # Number of BP lookups
system.cpu0.branchPred.condPredicted 13975310 # Number of conditional branches predicted
system.cpu0.branchPred.lookups 26894349 # Number of BP lookups
system.cpu0.branchPred.condPredicted 13975311 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 545296 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 16832825 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 12628735 # Number of BTB hits
@ -574,7 +574,7 @@ system.cpu0.numWorkItemsStarted 0 # nu
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 39965142 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 103919162 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 26894348 # Number of branches that fetch encountered
system.cpu0.fetch.Branches 26894349 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 19302280 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 61475471 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3204102 # Number of cycles fetch has spent squashing