gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 637714                       # Simulator instruction rate (inst/s)
host_mem_usage                                 154060                       # Number of bytes of host memory used
host_seconds                                  2853.60                       # Real time elapsed on the host
host_tick_rate                              886477792                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                  1819780129                       # Number of instructions simulated
sim_seconds                                  2.529655                       # Number of seconds simulated
sim_ticks                                2529654621000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              437373249                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency    89399351000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.016245                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses              7222414                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency  82176937000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses         7222414                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits             158839182                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   24252294000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.011755                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses             1889320                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency  22362974000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.011755                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses        1889320                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12473.108302                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               596212431                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency    113651645000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.015053                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               9111734                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 104539911000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.015053                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses          9111734                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12473.108302                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              596212431                       # number of overall hits
system.cpu.dcache.overall_miss_latency   113651645000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.015053                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              9111734                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 104539911000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.015053                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses         9111734                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                9107638                       # number of replacements
system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4078.970916                       # Cycle average of tags in use
system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle            40631938000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                  2244708                       # number of writebacks
system.cpu.icache.ReadReq_accesses         1819780130                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13987.531172                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits             1819779328                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       11218000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  802                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency     10416000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             802                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               2269051.531172                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses          1819780130                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13987.531172                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172                       # average overall mshr miss latency
system.cpu.icache.demand_hits              1819779328                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        11218000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   802                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     10416000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              802                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses         1819780130                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13987.531172                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits             1819779328                       # number of overall hits
system.cpu.icache.overall_miss_latency       11218000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  802                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     10416000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             802                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements                      1                       # number of replacements
system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                611.364745                       # Cycle average of tags in use
system.cpu.icache.total_refs               1819779328                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses           9112536                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits               6952383                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency   28074114000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.237053                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses             2160153                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency  23753808000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.237053                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses        2160153                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses         2244708                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits             2215611                       # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate       0.012962                       # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses             29097                       # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate     0.012962                       # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses        29097                       # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  4.244141                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses            9112536                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12996.354425                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                6952383                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency    28074114000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.237053                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses              2160153                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency  23753808000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.237053                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses         2160153                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses          11357244                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12823.621788                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits               9167994                       # number of overall hits
system.cpu.l2cache.overall_miss_latency   28074114000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.192762                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses             2189250                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency  23753808000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.190200                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses        2160153                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements               2127385                       # number of replacements
system.cpu.l2cache.sampled_refs               2160153                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             31194.155037                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 9167994                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          245730069000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                 1038202                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                     2529654621000                       # number of cpu cycles simulated
system.cpu.num_insts                       1819780129                       # Number of instructions executed
system.cpu.num_refs                         606571345                       # Number of memory references
system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls

---------- End Simulation Statistics   ----------