2011-03-18 01:20:22 +01:00
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---------- Begin Simulation Statistics ----------
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2011-05-05 03:38:28 +02:00
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host_inst_rate 157394 # Simulator instruction rate (inst/s)
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host_mem_usage 389256 # Number of bytes of host memory used
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host_seconds 329.61 # Real time elapsed on the host
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host_tick_rate 250791706 # Simulator tick rate (ticks/s)
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2011-03-18 01:20:22 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-05-05 03:38:28 +02:00
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sim_insts 51877985 # Number of instructions simulated
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sim_seconds 0.082663 # Number of seconds simulated
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sim_ticks 82662703500 # Number of ticks simulated
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2011-03-18 01:20:22 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-05-05 03:38:28 +02:00
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system.cpu.BPredUnit.BTBHits 9219891 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 11725604 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 157156 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 663969 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 11218057 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 13199466 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 789166 # Number of times the RAS was used to get a target.
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system.cpu.commit.branchMispredicts 640286 # The number of times a branch was mispredicted
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system.cpu.commit.branches 8429112 # Number of branches committed
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system.cpu.commit.bw_lim_events 798153 # number cycles where commit BW limit reached
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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2011-05-05 03:38:28 +02:00
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system.cpu.commit.commitCommittedInsts 52001215 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 2962888 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 16092788 # The number of squashed insts skipped by commit
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system.cpu.commit.committed_per_cycle::samples 93510390 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 0.556101 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 1.349439 # Number of insts commited each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-05-05 03:38:28 +02:00
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system.cpu.commit.committed_per_cycle::0 71869411 76.86% 76.86% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 10616143 11.35% 88.21% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 3483966 3.73% 91.94% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 1643130 1.76% 93.69% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 3524025 3.77% 97.46% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 741321 0.79% 98.25% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::6 539866 0.58% 98.83% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 294375 0.31% 99.15% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::8 798153 0.85% 100.00% # Number of insts commited each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-05-05 03:38:28 +02:00
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system.cpu.commit.committed_per_cycle::total 93510390 # Number of insts commited each cycle
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system.cpu.commit.count 52001215 # Number of instructions committed
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions.
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2011-05-05 03:38:28 +02:00
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system.cpu.commit.function_calls 530196 # Number of function calls committed.
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system.cpu.commit.int_insts 42424846 # Number of committed integer instructions.
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system.cpu.commit.loads 9179779 # Number of loads committed
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.membars 3 # Number of memory barriers committed
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2011-05-05 03:38:28 +02:00
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system.cpu.commit.refs 16257314 # Number of memory references committed
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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2011-05-05 03:38:28 +02:00
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system.cpu.committedInsts 51877985 # Number of Instructions Simulated
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system.cpu.committedInsts_total 51877985 # Number of Instructions Simulated
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system.cpu.cpi 3.186812 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 3.186812 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses::0 111585 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 111585 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.470534 # average LoadLockedReq miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11849.665522 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits::0 105103 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 105103 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 97071000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058090 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 6482 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 6482 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 951 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65540500 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049568 # mshr miss rate for LoadLockedReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.LoadLockedReq_mshr_misses 5531 # number of LoadLockedReq MSHR misses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.ReadReq_accesses::0 9397671 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 9397671 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 14774.624992 # average ReadReq miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13259.657075 # average ReadReq mshr miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.ReadReq_hits::0 8908615 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 8908615 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 7225619000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.052040 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 489056 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 489056 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 240430 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 3296695500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026456 # mshr miss rate for ReadReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 248626 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199517000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 105030 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 105030 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits::0 105030 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 105030 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses::0 6663090 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6663090 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 39945.828494 # average WriteReq miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38492.934326 # average WriteReq mshr miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.WriteReq_hits::0 4618865 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 4618865 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 81658261253 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.306798 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 2044225 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 2044225 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1873609 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 6567510483 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025606 # mshr miss rate for WriteReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.WriteReq_mshr_misses 170616 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 943852693 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 7367.210748 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 25538.461538 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 32.477815 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 949 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 6991483 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 664000 # number of cycles access was blocked
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.demand_accesses::0 16060761 # number of demand (read+write) accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.demand_accesses::total 16060761 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 35086.467018 # average overall miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.demand_avg_mshr_miss_latency 23528.668366 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 13527480 # number of demand (read+write) hits
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.demand_hits::total 13527480 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 88883880253 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.157731 # miss rate for demand accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.demand_misses::0 2533281 # number of demand (read+write) misses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.demand_misses::total 2533281 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2114039 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 9864205983 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.026103 # mshr miss rate for demand accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.demand_mshr_misses 419242 # number of demand (read+write) MSHR misses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.occ_blocks::0 511.750766 # Average occupied blocks per context
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2011-04-20 03:45:23 +02:00
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system.cpu.dcache.occ_percent::0 0.999513 # Average percentage of cache occupancy
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.overall_accesses::0 16060761 # number of overall (read+write) accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.overall_accesses::total 16060761 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 35086.467018 # average overall miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-05-05 03:38:28 +02:00
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system.cpu.dcache.overall_avg_mshr_miss_latency 23528.668366 # average overall mshr miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.overall_hits::0 13527480 # number of overall hits
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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2011-05-05 03:38:28 +02:00
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system.cpu.dcache.overall_hits::total 13527480 # number of overall hits
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system.cpu.dcache.overall_miss_latency 88883880253 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.157731 # miss rate for overall accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-05-05 03:38:28 +02:00
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system.cpu.dcache.overall_misses::0 2533281 # number of overall misses
|
2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
2011-05-05 03:38:28 +02:00
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system.cpu.dcache.overall_misses::total 2533281 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2114039 # number of overall MSHR hits
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|
|
|
system.cpu.dcache.overall_mshr_miss_latency 9864205983 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0.026103 # mshr miss rate for overall accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 419242 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 39143369693 # number of overall MSHR uncacheable cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.dcache.replacements 422530 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 423042 # Sample count of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.dcache.tagsinuse 511.750766 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 13739480 # Total number of references to valid blocks.
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit.
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.dcache.writebacks 390905 # number of writebacks
|
|
|
|
|
system.cpu.decode.BlockedCycles 53935385 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.BranchMispred 70801 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.BranchResolved 1222673 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DecodedInsts 76253610 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.IdleCycles 23916717 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.RunCycles 14472094 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.SquashCycles 2561252 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.SquashedInsts 234958 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.UnblockCycles 1186166 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.dtb.accesses 35208809 # DTB accesses
|
|
|
|
|
system.cpu.dtb.align_faults 1597 # Number of TLB faults due to alignment restrictions
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.dtb.flush_entries 2756 # Number of entries that have been flushed from TLB
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.dtb.hits 35136197 # DTB hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.dtb.misses 72612 # DTB misses
|
|
|
|
|
system.cpu.dtb.perms_faults 1160 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 1027 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dtb.read_accesses 27716932 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.read_hits 27655119 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 61813 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 7491877 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.write_hits 7481078 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 10799 # DTB write misses
|
|
|
|
|
system.cpu.fetch.Branches 13199466 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 6541408 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 16046672 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 257127 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 63922910 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.ItlbSquashes 4120 # Number of outstanding ITLB misses that were squashed
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 17774 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.SquashCycles 1040401 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.TlbCycles 7293 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu.fetch.branchRate 0.079839 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 6539916 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 10009057 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.386649 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 96071614 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 0.819308 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.074078 # Number of instructions fetched each cycle (Total)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.fetch.rateDist::0 80041495 83.31% 83.31% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 1277020 1.33% 84.64% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 1747355 1.82% 86.46% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 1275318 1.33% 87.79% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 4729503 4.92% 92.71% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 796752 0.83% 93.54% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 838393 0.87% 94.41% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 743786 0.77% 95.19% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 4621992 4.81% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.fetch.rateDist::total 96071614 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fp_regfile_reads 5589 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 1920 # number of floating regfile writes
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::0 6541316 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 6541316 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14764.035941 # average ReadReq miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12016.810358 # average ReadReq mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.ReadReq_hits::0 5995343 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 5995343 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 8060764995 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.083465 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::0 545973 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 545973 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 43426 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 6039011995 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076827 # mshr miss rate for ReadReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 502547 # number of ReadReq MSHR misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency 4957500 # number of ReadReq MSHR uncacheable cycles
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 7482.701149 # average number of cycles each access was blocked
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.avg_refs 11.930746 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 87 # number of cycles access was blocked
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 650995 # number of cycles access was blocked
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.demand_accesses::0 6541316 # number of demand (read+write) accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.demand_accesses::total 6541316 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::0 14764.035941 # average overall miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 12016.810358 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits::0 5995343 # number of demand (read+write) hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.demand_hits::total 5995343 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 8060764995 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate::0 0.083465 # miss rate for demand accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.demand_misses::0 545973 # number of demand (read+write) misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.demand_misses::total 545973 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 43426 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 6039011995 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.076827 # mshr miss rate for demand accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 502547 # number of demand (read+write) MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 496.616847 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.969955 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.overall_accesses::0 6541316 # number of overall (read+write) accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.overall_accesses::total 6541316 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::0 14764.035941 # average overall miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 12016.810358 # average overall mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.overall_hits::0 5995343 # number of overall hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.overall_hits::total 5995343 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 8060764995 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate::0 0.083465 # miss rate for overall accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.overall_misses::0 545973 # number of overall misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.overall_misses::total 545973 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 43426 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 6039011995 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.076827 # mshr miss rate for overall accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 502547 # number of overall MSHR misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 4957500 # number of overall MSHR uncacheable cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.replacements 502000 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 502512 # Sample count of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.tagsinuse 496.616847 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 5995343 # Total number of references to valid blocks.
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.warmup_cycle 6206760000 # Cycle when the warmup percentage was hit.
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.icache.writebacks 41552 # number of writebacks
|
|
|
|
|
system.cpu.idleCycles 69253794 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.branchMispredicts 710007 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.exec_branches 10210898 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_nop 166890 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.475154 # Inst execution rate
|
|
|
|
|
system.cpu.iew.exec_refs 35938773 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_stores 7790783 # Number of stores executed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 21412394 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 12805909 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 4002276 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 355591 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 8720984 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 70347510 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 28147990 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1057037 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 78555101 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 28690 # Number of times the IQ has become full, causing a stall
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 45651 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 2561252 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 263680 # Number of cycles IEW is unblocking
|
2011-04-22 19:18:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 8400 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 328416 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7668 # Number of memory responses ignored because the instruction is squashed
|
2011-04-22 19:18:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 280189 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 17001194 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 3626130 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 1643449 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 280189 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 185530 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 524477 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.wb_consumers 62170053 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_count 60762788 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_fanout 0.510007 # average fanout of values written-back
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iew.wb_producers 31707186 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_rate 0.367534 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_sent 78030912 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.int_regfile_reads 182505983 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 43793404 # number of integer regfile writes
|
|
|
|
|
system.cpu.ipc 0.313793 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.313793 # IPC: Total IPC of All Threads
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 2393223 3.01% 3.01% # Type of FU issued
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 40692276 51.11% 54.12% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 71186 0.09% 54.21% # Type of FU issued
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 15 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.21% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 881 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.21% # Type of FU issued
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 28499876 35.80% 90.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 7954659 9.99% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 79612138 # Type of FU issued
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 8660 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 16534 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 6417 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 9494 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 4821134 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.060558 # FU busy rate (busy events/executed inst)
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 5360 0.11% 0.11% # attempts to use FU when none available
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.fu_full::MemRead 4502804 93.40% 93.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 312970 6.49% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 82031389 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 260297363 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 60756371 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 88040036 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 66148270 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 79612138 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 4032350 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 17603379 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 124488 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1069462 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 22177627 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 96071614 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.828675 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.378358 # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::0 59906627 62.36% 62.36% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 16708495 17.39% 79.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 7171843 7.47% 87.21% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 4115905 4.28% 91.50% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 5939256 6.18% 97.68% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 1302334 1.36% 99.03% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 619107 0.64% 99.68% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 235470 0.25% 99.92% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 72577 0.08% 100.00% # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::total 96071614 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.rate 0.481548 # Inst issue rate
|
|
|
|
|
system.cpu.itb.accesses 6554572 # DTB accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.itb.flush_entries 1626 # Number of entries that have been flushed from TLB
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.itb.hits 6547279 # DTB hits
|
|
|
|
|
system.cpu.itb.inst_accesses 6554572 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 6547279 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 7293 # ITB inst misses
|
|
|
|
|
system.cpu.itb.misses 7293 # DTB misses
|
|
|
|
|
system.cpu.itb.perms_faults 5323 # Number of TLB faults due to permissions restrictions
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 527 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 1505 # Number of conflicting stores.
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.memDep0.insertedLoads 12805909 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 8720984 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.misc_regfile_reads 84139545 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 512625 # number of misc regfile writes
|
|
|
|
|
system.cpu.numCycles 165325408 # number of cpu cycles simulated
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.rename.BlockCycles 33120031 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.CommittedMaps 36654067 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.IQFullEvents 775523 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.IdleCycles 25553608 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.LSQFullEvents 2458566 # Number of times rename has blocked due to LSQ full
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.rename.ROBFullEvents 439444 # Number of times rename has blocked due to ROB full
|
2011-05-05 03:38:28 +02:00
|
|
|
system.cpu.rename.RenameLookups 190069366 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RenamedInsts 73481256 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RenamedOperands 53179946 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RunCycles 13052599 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.SquashCycles 2561252 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.UnblockCycles 5439754 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.UndoneMaps 16525878 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 50199 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.int_rename_lookups 190019167 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.serializeStallCycles 16344370 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.serializingInsts 812158 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 14266692 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 663049 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rob.rob_reads 159865147 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 138793846 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1093874 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.writebacks 0 # number of writebacks
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.ReadExReq_accesses::0 168913 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 168913 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52452.525224 # average ReadExReq miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40011.488822 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_hits::0 60982 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 60982 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 5661253500 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::0 0.638974 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses::0 107931 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 107931 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 4318480000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.638974 # mshr miss rate for ReadExReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.ReadExReq_mshr_misses 107931 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses::0 754170 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::1 103109 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 857279 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::0 52487.372499 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::1 12162755.681818 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 12215243.054317 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40042.547465 # average ReadReq mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.ReadReq_hits::0 733778 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::1 103021 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 836799 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 1070322500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate::0 0.027039 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::1 0.000853 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 0.027892 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses::0 20392 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::1 88 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.l2c.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency 818309500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.027097 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::1 0.198198 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.225295 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses 20436 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 28946013500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.UpgradeReq_accesses::0 1731 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 1731 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 430.514488 # average UpgradeReq miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.591366 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_hits::0 40 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::0 0.976892 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_misses::0 1691 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 1691 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 67641000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.976892 # mshr miss rate for UpgradeReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.UpgradeReq_mshr_misses 1691 # number of UpgradeReq MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 748185950 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.Writeback_accesses::0 432457 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 432457 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits::0 432457 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 432457 # number of Writeback hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.avg_refs 8.161920 # Average number of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.demand_accesses::0 923083 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::1 103109 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 1026192 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency::0 52458.062857 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::1 76495181.818182 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 76547639.881039 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40016.433351 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits::0 794760 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::1 103021 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 897781 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 6731576000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate::0 0.139016 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::1 0.000853 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.139869 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_misses::0 128323 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::1 88 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 128411 # number of demand (read+write) misses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.l2c.demand_mshr_hits 44 # number of demand (read+write) MSHR hits
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.demand_mshr_miss_latency 5136789500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::0 0.139063 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::1 1.244964 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 1.384027 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_misses 128367 # number of demand (read+write) MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.occ_blocks::0 6522.284105 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::1 31526.690965 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_percent::0 0.099522 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::1 0.481059 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.overall_accesses::0 923083 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::1 103109 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 1026192 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency::0 52458.062857 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::1 76495181.818182 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 76547639.881039 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40016.433351 # average overall mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.overall_hits::0 794760 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::1 103021 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 897781 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 6731576000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate::0 0.139016 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::1 0.000853 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.139869 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_misses::0 128323 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::1 88 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 128411 # number of overall misses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.l2c.overall_mshr_hits 44 # number of overall MSHR hits
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.overall_mshr_miss_latency 5136789500 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::0 0.139063 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::1 1.244964 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 1.384027 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_misses 128367 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 29694199450 # number of overall MSHR uncacheable cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.replacements 94647 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 126884 # Sample count of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.tagsinuse 38048.975070 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1035617 # Total number of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-05-05 03:38:28 +02:00
|
|
|
system.l2c.writebacks 87762 # number of writebacks
|
2011-03-18 01:20:22 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
