2011-03-18 01:20:22 +01:00
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---------- Begin Simulation Statistics ----------
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2011-04-04 18:42:25 +02:00
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host_inst_rate 136397 # Simulator instruction rate (inst/s)
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host_mem_usage 350148 # Number of bytes of host memory used
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host_seconds 380.99 # Real time elapsed on the host
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host_tick_rate 218804000 # Simulator tick rate (ticks/s)
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2011-03-18 01:20:22 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-04-04 18:42:25 +02:00
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sim_insts 51966326 # Number of instructions simulated
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sim_seconds 0.083363 # Number of seconds simulated
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sim_ticks 83363125500 # Number of ticks simulated
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2011-03-18 01:20:22 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-04-04 18:42:25 +02:00
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system.cpu.BPredUnit.BTBHits 9109525 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 11661597 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 155432 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 643707 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 11148181 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 13121145 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 795550 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 8359370 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 811751 # number cycles where commit BW limit reached
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2011-04-04 18:42:25 +02:00
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system.cpu.commit.COM:committed_per_cycle::samples 94793091 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.549507 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.345543 # Number of insts commited each cycle
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-04-04 18:42:25 +02:00
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system.cpu.commit.COM:committed_per_cycle::0 73158899 77.18% 77.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 10643869 11.23% 88.41% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 3426640 3.61% 92.02% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 1618432 1.71% 93.73% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 3558653 3.75% 97.48% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 736107 0.78% 98.26% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 543274 0.57% 98.83% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 295466 0.31% 99.14% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 811751 0.86% 100.00% # Number of insts commited each cycle
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-04-04 18:42:25 +02:00
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system.cpu.commit.COM:committed_per_cycle::total 94793091 # Number of insts commited each cycle
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system.cpu.commit.COM:count 52089506 # Number of instructions committed
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions.
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2011-04-04 18:42:25 +02:00
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system.cpu.commit.COM:function_calls 529550 # Number of function calls committed.
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system.cpu.commit.COM:int_insts 42498657 # Number of committed integer instructions.
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system.cpu.commit.COM:loads 9209715 # Number of loads committed
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:membars 3 # Number of memory barriers committed
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2011-04-04 18:42:25 +02:00
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system.cpu.commit.COM:refs 16294715 # Number of memory references committed
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2011-04-04 18:42:25 +02:00
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system.cpu.commit.branchMispredicts 710936 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 52089506 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 2963004 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 16584310 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 51966326 # Number of Instructions Simulated
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system.cpu.committedInsts_total 51966326 # Number of Instructions Simulated
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system.cpu.cpi 3.208352 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 3.208352 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses::0 110398 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 110398 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14987.700535 # average LoadLockedReq miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11878.197102 # average LoadLockedReq mshr miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.LoadLockedReq_hits::0 103853 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 103853 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 98094500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.059285 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 6545 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 6545 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 954 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66411000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050644 # mshr miss rate for LoadLockedReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.LoadLockedReq_mshr_misses 5591 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 312483000 # number of LoadLockedReq MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_accesses::0 9405887 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 9405887 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 14818.902196 # average ReadReq miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13268.493454 # average ReadReq mshr miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.ReadReq_hits::0 8919589 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 8919589 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 7206402500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.051701 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 486298 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 486298 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 238048 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 3293903500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026393 # mshr miss rate for ReadReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 248250 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38193579000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 105006 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 105006 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits::0 105006 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 105006 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses::0 6670914 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6670914 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 39947.948992 # average WriteReq miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38533.384242 # average WriteReq mshr miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_hits::0 4625272 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 4625272 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 81719202272 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.306651 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 2045642 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 2045642 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1875083 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 6572215483 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025568 # mshr miss rate for WriteReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_mshr_misses 170559 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939908183 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 7476.302863 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 21020 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 32.546615 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 908 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 6788483 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 525500 # number of cycles access was blocked
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_accesses::0 16076801 # number of demand (read+write) accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_accesses::total 16076801 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 35121.529251 # average overall miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_avg_mshr_miss_latency 23557.561998 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 13544861 # number of demand (read+write) hits
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_hits::total 13544861 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 88925604772 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.157490 # miss rate for demand accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_misses::0 2531940 # number of demand (read+write) misses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_misses::total 2531940 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2113131 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 9866118983 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.026051 # mshr miss rate for demand accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_mshr_misses 418809 # number of demand (read+write) MSHR misses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.occ_%::0 0.999517 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 511.752645 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses::0 16076801 # number of overall (read+write) accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_accesses::total 16076801 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 35121.529251 # average overall miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_avg_mshr_miss_latency 23557.561998 # average overall mshr miss latency
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_hits::0 13544861 # number of overall hits
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_hits::total 13544861 # number of overall hits
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system.cpu.dcache.overall_miss_latency 88925604772 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.157490 # miss rate for overall accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_misses::0 2531940 # number of overall misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.overall_misses::total 2531940 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 2113131 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 9866118983 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0.026051 # mshr miss rate for overall accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 418809 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 39133487183 # number of overall MSHR uncacheable cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.replacements 422131 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 422643 # Sample count of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.tagsinuse 511.752645 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 13755599 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 48259000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 390426 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 54881827 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 71596 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 1214700 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 77864847 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 24077327 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 14646912 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 2655366 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 235100 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 1186997 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.dtb.accesses 35220915 # DTB accesses
|
|
|
|
|
system.cpu.dtb.align_faults 1535 # Number of TLB faults due to alignment restrictions
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.flush_entries 2767 # Number of entries that have been flushed from TLB
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.hits 35140303 # DTB hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.misses 80612 # DTB misses
|
|
|
|
|
system.cpu.dtb.perms_faults 1012 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 1019 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dtb.read_accesses 27731873 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.read_hits 27661932 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 69941 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 7489042 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.write_hits 7478371 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 10671 # DTB write misses
|
|
|
|
|
system.cpu.fetch.Branches 13121145 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 6614824 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 16225603 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 267333 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 65526878 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.ItlbSquashes 4933 # Number of outstanding ITLB misses that were squashed
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 21202 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.SquashCycles 1110741 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.TlbCycles 8007 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu.fetch.branchRate 0.078699 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 6613458 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 9905075 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.393021 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 97448429 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 0.824712 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.089384 # Number of instructions fetched each cycle (Total)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.fetch.rateDist::0 81239523 83.37% 83.37% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 1275012 1.31% 84.68% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 1734122 1.78% 86.45% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 1277387 1.31% 87.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 4689721 4.81% 92.58% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 799978 0.82% 93.40% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 845081 0.87% 94.27% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 738625 0.76% 95.02% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 4848980 4.98% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.fetch.rateDist::total 97448429 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fp_regfile_reads 5433 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 1933 # number of floating regfile writes
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::0 6614731 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 6614731 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14762.027587 # average ReadReq miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12010.787096 # average ReadReq mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_hits::0 6061711 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 6061711 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 8163696496 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.083604 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::0 553020 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 553020 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 43430 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 6120576996 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.077039 # mshr miss rate for ReadReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 509590 # number of ReadReq MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency 4968000 # number of ReadReq MSHR uncacheable cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 6801.619835 # average number of cycles each access was blocked
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.avg_refs 11.895551 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 822996 # number of cycles access was blocked
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_accesses::0 6614731 # number of demand (read+write) accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_accesses::total 6614731 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::0 14762.027587 # average overall miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 12010.787096 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits::0 6061711 # number of demand (read+write) hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_hits::total 6061711 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 8163696496 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate::0 0.083604 # miss rate for demand accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_misses::0 553020 # number of demand (read+write) misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_misses::total 553020 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 43430 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 6120576996 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.077039 # mshr miss rate for demand accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 509590 # number of demand (read+write) MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.969182 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 496.221044 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses::0 6614731 # number of overall (read+write) accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_accesses::total 6614731 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::0 14762.027587 # average overall miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 12010.787096 # average overall mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_hits::0 6061711 # number of overall hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_hits::total 6061711 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 8163696496 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate::0 0.083604 # miss rate for overall accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_misses::0 553020 # number of overall misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_misses::total 553020 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 43430 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 6120576996 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.077039 # mshr miss rate for overall accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 509590 # number of overall MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 4968000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.replacements 509066 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 509578 # Sample count of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.tagsinuse 496.221044 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 6061711 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 6357615000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 41956 # number of writebacks
|
|
|
|
|
system.cpu.idleCycles 69277823 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 10103883 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 231467 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.472681 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 35943577 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 7792930 # Number of stores executed
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.WB:consumers 62506487 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 60999387 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.509822 # average fanout of values written-back
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.WB:producers 31867154 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.365866 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 78280633 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 793572 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 21409899 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 12831645 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 4013649 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 440829 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 8731029 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 70887049 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 28150647 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1185759 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 78808302 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 28695 # Number of times the IQ has become full, causing a stall
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 45726 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 2655366 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 263937 # Number of cycles IEW is unblocking
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 8278 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 328988 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 7892 # Number of memory responses ignored because the instruction is squashed
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 280623 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 17006286 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 3621930 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1646029 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 280623 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 286587 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 506985 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.int_regfile_reads 183036764 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 44051569 # number of integer regfile writes
|
|
|
|
|
system.cpu.ipc 0.311687 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.311687 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 2.99% 2.99% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 41025492 51.29% 54.28% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 89631 0.11% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 14 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 9 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 1 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 882 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 10 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 28522924 35.66% 90.05% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7962144 9.95% 100.00% # Type of FU issued
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 79994061 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 4819476 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.060248 # FU busy rate (busy events/executed inst)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 5122 0.11% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 4502393 93.42% 93.53% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 311961 6.47% 100.00% # attempts to use FU when none available
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 97448429 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.820886 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.375646 # Number of insts issued each cycle
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 61152445 62.75% 62.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 16744626 17.18% 79.94% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 7216759 7.41% 87.34% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 4112834 4.22% 91.56% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 5964384 6.12% 97.68% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 1312092 1.35% 99.03% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 631511 0.65% 99.68% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 239871 0.25% 99.92% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 73907 0.08% 100.00% # Number of insts issued each cycle
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 97448429 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 0.479793 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 8478 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 16113 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 6290 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 9126 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.int_alu_accesses 82412108 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 262450164 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 60993097 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 88832185 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 66612352 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 79994061 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 4043230 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 17919898 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 129886 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1080226 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 22542223 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.itb.accesses 6629825 # DTB accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.itb.flush_entries 1593 # Number of entries that have been flushed from TLB
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.itb.hits 6621818 # DTB hits
|
|
|
|
|
system.cpu.itb.inst_accesses 6629825 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 6621818 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 8007 # ITB inst misses
|
|
|
|
|
system.cpu.itb.misses 8007 # DTB misses
|
|
|
|
|
system.cpu.itb.perms_faults 6553 # Number of TLB faults due to permissions restrictions
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 3412 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 10055 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 12831645 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 8731029 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.misc_regfile_reads 85580617 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 661928 # number of misc regfile writes
|
|
|
|
|
system.cpu.numCycles 166726252 # number of cpu cycles simulated
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.rename.RENAME:BlockCycles 33115020 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 36897186 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 774970 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 25771675 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 2462995 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 448472 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 192653284 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 74465658 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 54282132 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 13171967 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 2655366 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 5478763 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 17384945 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:fp_rename_lookups 47581 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.RENAME:int_rename_lookups 192605703 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 17255638 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 861623 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 14920123 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 719344 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rob.rob_reads 161714856 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 140047516 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1095909 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
|
|
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency 234200000 # number of LoadLockedReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadExReq_accesses::0 168831 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 168831 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52452.308619 # average ReadExReq miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40012.249340 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_hits::0 60866 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 60866 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 5663013500 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::0 0.639486 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses::0 107965 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 107965 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 4319922500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.639486 # mshr miss rate for ReadExReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.ReadExReq_mshr_misses 107965 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses::0 760970 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::1 118352 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 879322 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::0 52680.502591 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::1 6692714.285714 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 6745394.788305 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40041.751725 # average ReadReq mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.ReadReq_hits::0 740516 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::1 118191 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 858707 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 1077527000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate::0 0.026879 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::1 0.001360 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 0.028239 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses::0 20454 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::1 161 # number of ReadReq misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.ReadReq_misses::total 20615 # number of ReadReq misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency 823819000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.027037 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::1 0.173837 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.200874 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses 20574 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 28941133500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.UpgradeReq_accesses::0 1757 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 1757 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 817.335660 # average UpgradeReq miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.581734 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 1405000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::0 0.978372 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_misses::0 1719 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 1719 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 68761000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.978372 # mshr miss rate for UpgradeReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.UpgradeReq_mshr_misses 1719 # number of UpgradeReq MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 746054947 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.Writeback_accesses::0 432382 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 432382 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits::0 432382 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 432382 # number of Writeback hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.avg_refs 8.321857 # Average number of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.demand_accesses::0 929801 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::1 118352 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 1048153 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency::0 52488.654327 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::1 41866711.180124 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 41919199.834451 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40016.971503 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits::0 801382 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::1 118191 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 919573 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 6740540500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate::0 0.138114 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::1 0.001360 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.139475 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_misses::0 128419 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::1 161 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 128580 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_mshr_hits 41 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_miss_latency 5143741500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::0 0.138244 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::1 1.086074 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 1.224317 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_misses 128539 # number of demand (read+write) MSHR misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.occ_%::0 0.099437 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::1 0.480717 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_blocks::0 6516.698147 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::1 31504.278077 # Average occupied blocks per context
|
|
|
|
|
system.l2c.overall_accesses::0 929801 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::1 118352 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 1048153 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency::0 52488.654327 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::1 41866711.180124 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 41919199.834451 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40016.971503 # average overall mshr miss latency
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.overall_hits::0 801382 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::1 118191 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 919573 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 6740540500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate::0 0.138114 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::1 0.001360 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.139475 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_misses::0 128419 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::1 161 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 128580 # number of overall misses
|
|
|
|
|
system.l2c.overall_mshr_hits 41 # number of overall MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_miss_latency 5143741500 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::0 0.138244 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::1 1.086074 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 1.224317 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_misses 128539 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 29687188447 # number of overall MSHR uncacheable cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.replacements 94739 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 127041 # Sample count of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.tagsinuse 38020.976224 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1057217 # Total number of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-04-04 18:42:25 +02:00
|
|
|
system.l2c.writebacks 87634 # number of writebacks
|
2011-03-18 01:20:22 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
