2009-05-11 19:38:46 +02:00
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---------- Begin Simulation Statistics ----------
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2012-09-10 17:57:47 +02:00
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sim_seconds 0.000108 # Number of seconds simulated
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sim_ticks 107952 # Number of ticks simulated
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final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-06-10 09:45:24 +02:00
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sim_freq 1000000000 # Frequency of simulated ticks
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2013-06-10 13:46:20 +02:00
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host_inst_rate 37306 # Simulator instruction rate (inst/s)
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host_op_rate 37301 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 755806 # Simulator tick rate (ticks/s)
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host_mem_usage 148468 # Number of bytes of host memory used
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host_seconds 0.14 # Real time elapsed on the host
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2012-08-15 16:38:05 +02:00
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sim_insts 5327 # Number of instructions simulated
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sim_ops 5327 # Number of ops (including micro ops) simulated
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2013-05-21 18:32:57 +02:00
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system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
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system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
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system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
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2013-06-10 13:46:20 +02:00
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system.ruby.dir_cntrl0.memBuffer.memReq 2574 # Total number of memory requests
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system.ruby.dir_cntrl0.memBuffer.memRead 1289 # Number of memory reads
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system.ruby.dir_cntrl0.memBuffer.memWrite 1285 # Number of memory writes
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system.ruby.dir_cntrl0.memBuffer.memRefresh 750 # Number of memory refreshes
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system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1871 # Delay stalled at the head of the bank queue
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system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
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system.ruby.dir_cntrl0.memBuffer.totalStalls 1873 # Total number of stall cycles
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system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.727661 # Expected number of stall cycles per request
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system.ruby.dir_cntrl0.memBuffer.memBankBusy 758 # memory stalls due to busy bank
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system.ruby.dir_cntrl0.memBuffer.memBusBusy 992 # memory stalls due to busy bus
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system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround
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system.ruby.dir_cntrl0.memBuffer.memArbWait 69 # memory stalls due to arbitration
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system.ruby.dir_cntrl0.memBuffer.memBankCount | 166 6.45% 6.45% | 40 1.55% 8.00% | 36 1.40% 9.40% | 48 1.86% 11.27% | 109 4.23% 15.50% | 42 1.63% 17.13% | 63 2.45% 19.58% | 241 9.36% 28.94% | 50 1.94% 30.89% | 34 1.32% 32.21% | 16 0.62% 32.83% | 26 1.01% 33.84% | 60 2.33% 36.17% | 64 2.49% 38.66% | 38 1.48% 40.13% | 46 1.79% 41.92% | 30 1.17% 43.08% | 88 3.42% 46.50% | 202 7.85% 54.35% | 144 5.59% 59.95% | 40 1.55% 61.50% | 58 2.25% 63.75% | 22 0.85% 64.61% | 20 0.78% 65.38% | 60 2.33% 67.72% | 120 4.66% 72.38% | 136 5.28% 77.66% | 125 4.86% 82.52% | 84 3.26% 85.78% | 134 5.21% 90.99% | 166 6.45% 97.44% | 66 2.56% 100.00% # Number of accesses per bank
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system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2574 # Number of accesses per bank
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2011-06-10 09:45:24 +02:00
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system.cpu.workload.num_syscalls 11 # Number of system calls
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2012-09-10 17:57:47 +02:00
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system.cpu.numCycles 107952 # number of cpu cycles simulated
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2011-02-08 04:23:13 +01:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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2011-06-10 09:45:24 +02:00
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-08-15 16:38:05 +02:00
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system.cpu.committedInsts 5327 # Number of instructions committed
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system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
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2011-06-10 09:45:24 +02:00
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 146 # number of times a function call or return occured
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2012-08-15 16:38:05 +02:00
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system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
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system.cpu.num_int_insts 4505 # number of integer instructions
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2011-06-10 09:45:24 +02:00
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system.cpu.num_fp_insts 0 # number of float instructions
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2012-08-15 16:38:05 +02:00
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system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
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system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
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2011-06-10 09:45:24 +02:00
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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2012-08-15 16:38:05 +02:00
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system.cpu.num_mem_refs 1401 # number of memory refs
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system.cpu.num_load_insts 723 # Number of load instructions
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2011-02-08 04:23:13 +01:00
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system.cpu.num_store_insts 678 # Number of store instructions
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2011-06-10 09:45:24 +02:00
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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2012-09-10 17:57:47 +02:00
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system.cpu.num_busy_cycles 107952 # Number of busy cycles
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2011-06-10 09:45:24 +02:00
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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2013-06-10 13:46:20 +02:00
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system.ruby.l1_cntrl0.Load 715 0.00% 0.00%
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system.ruby.l1_cntrl0.Ifetch 5370 0.00% 0.00%
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system.ruby.l1_cntrl0.Store 673 0.00% 0.00%
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system.ruby.l1_cntrl0.Data 1289 0.00% 0.00%
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system.ruby.l1_cntrl0.Replacement 1285 0.00% 0.00%
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system.ruby.l1_cntrl0.Writeback_Ack 1285 0.00% 0.00%
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system.ruby.l1_cntrl0.I.Load 395 0.00% 0.00%
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system.ruby.l1_cntrl0.I.Ifetch 715 0.00% 0.00%
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system.ruby.l1_cntrl0.I.Store 179 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Load 320 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Ifetch 4655 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Store 494 0.00% 0.00%
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system.ruby.l1_cntrl0.M.Replacement 1285 0.00% 0.00%
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system.ruby.l1_cntrl0.MI.Writeback_Ack 1285 0.00% 0.00%
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system.ruby.l1_cntrl0.IS.Data 1110 0.00% 0.00%
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system.ruby.l1_cntrl0.IM.Data 179 0.00% 0.00%
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system.ruby.dir_cntrl0.GETX 1289 0.00% 0.00%
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system.ruby.dir_cntrl0.PUTX 1285 0.00% 0.00%
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system.ruby.dir_cntrl0.Memory_Data 1289 0.00% 0.00%
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system.ruby.dir_cntrl0.Memory_Ack 1285 0.00% 0.00%
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system.ruby.dir_cntrl0.I.GETX 1289 0.00% 0.00%
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system.ruby.dir_cntrl0.M.PUTX 1285 0.00% 0.00%
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system.ruby.dir_cntrl0.IM.Memory_Data 1289 0.00% 0.00%
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system.ruby.dir_cntrl0.MI.Memory_Ack 1285 0.00% 0.00%
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2009-05-11 19:38:46 +02:00
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---------- End Simulation Statistics ----------
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