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gem5/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout

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stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simerr
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 23:00:18 +02:00
M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
M5 compiled Aug 26 2010 13:03:41
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:03:47
BPRED: Update regressions for tournament predictor fix.
2010-05-14 05:45:59 +02:00
M5 executing on zizzer
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 23:00:18 +02:00
Global frequency set at 1000000000000 ticks per second
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 17:11:42 +01:00
info: Entering event queue @ 0. Starting simulation...
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
Begining test of difficult SPARC instructions...
LDSTUB: Passed
SWAP: Passed
CAS FAIL: Passed
CAS WORK: Passed
CASX FAIL: Passed
CASX WORK: Passed
LDTX: Passed
LDTW: Passed
STTW: Passed
Done
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
Exiting @ tick 27419000 because target called exit()
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