2009-05-12 21:01:16 +02:00
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---------- Begin Simulation Statistics ----------
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2011-06-20 03:43:42 +02:00
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sim_seconds 0.042094 # Number of seconds simulated
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sim_ticks 42094188000 # Number of ticks simulated
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2009-05-12 21:01:16 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-06-20 03:43:42 +02:00
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host_inst_rate 121365 # Simulator instruction rate (inst/s)
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host_tick_rate 55588778 # Simulator tick rate (ticks/s)
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host_mem_usage 196912 # Number of bytes of host memory used
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host_seconds 757.24 # Real time elapsed on the host
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2011-02-18 20:31:37 +01:00
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sim_insts 91903056 # Number of instructions simulated
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2011-06-20 03:43:42 +02:00
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 19996214 # DTB read hits
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system.cpu.dtb.read_misses 10 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 19996224 # DTB read accesses
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system.cpu.dtb.write_hits 6501905 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 6501928 # DTB write accesses
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system.cpu.dtb.data_hits 26498119 # DTB hits
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system.cpu.dtb.data_misses 33 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 26498152 # DTB accesses
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system.cpu.itb.fetch_hits 10077672 # ITB hits
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system.cpu.itb.fetch_misses 49 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 10077721 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 389 # Number of system calls
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system.cpu.numCycles 84188377 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 83816425 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 10559 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 7701629 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 76486748 # Number of cycles cpu stages are processed.
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system.cpu.activity 90.851909 # Percentage of cycles cpu is active
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2010-11-08 20:58:24 +01:00
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system.cpu.comLoads 19996198 # Number of Load instructions committed
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system.cpu.comStores 6501103 # Number of Store instructions committed
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2011-06-20 03:43:42 +02:00
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system.cpu.comBranches 10240685 # Number of Branches instructions committed
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system.cpu.comNops 7723346 # Number of Nop instructions committed
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system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
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system.cpu.comInts 43665352 # Number of Integer instructions committed
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system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
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2011-02-18 20:31:37 +01:00
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system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
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2011-06-20 03:43:42 +02:00
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
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2011-02-18 20:31:37 +01:00
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system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
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2011-06-20 03:43:42 +02:00
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system.cpu.cpi 0.916056 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.916056 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.091636 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.091636 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 13660151 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 10092693 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 4598416 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 8981993 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 4278316 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 131 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 47.632146 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 6418014 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 7242137 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 73810840 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 136386312 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 2206031 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 8057919 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 38650469 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 26688179 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 3946440 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 651118 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 4597558 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 5643144 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 44.894950 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 57370437 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.stage0.idleCycles 27496111 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 56692266 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 67.339778 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 34731944 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 49456433 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 58.744965 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 34177132 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 50011245 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 59.403978 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 66154944 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 18033433 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 21.420336 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 30219873 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 53968504 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 64.104459 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 7205 # number of replacements
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system.cpu.icache.tagsinuse 1491.617776 # Cycle average of tags in use
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system.cpu.icache.total_refs 10066620 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 9090 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1107.438944 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 1491.617776 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.728329 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 10066620 # number of ReadReq hits
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system.cpu.icache.demand_hits 10066620 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 10066620 # number of overall hits
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system.cpu.icache.ReadReq_misses 11049 # number of ReadReq misses
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system.cpu.icache.demand_misses 11049 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 11049 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 285327000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 285327000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 285327000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 10077669 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 10077669 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 10077669 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 25823.784958 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 25823.784958 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 25823.784958 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 13900 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_mshr_hits 1959 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits 1959 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 1959 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 9090 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 9090 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 9090 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 218831500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 218831500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 218831500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000902 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.000902 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.000902 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 24073.872387 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
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system.cpu.dcache.replacements 157 # number of replacements
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system.cpu.dcache.tagsinuse 1441.601089 # Cycle average of tags in use
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system.cpu.dcache.total_refs 26491207 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 11916.872245 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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|
|
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system.cpu.dcache.occ_blocks::0 1441.601089 # Average occupied blocks per context
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|
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system.cpu.dcache.occ_percent::0 0.351953 # Average percentage of cache occupancy
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|
|
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system.cpu.dcache.ReadReq_hits 19995646 # number of ReadReq hits
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|
|
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system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits
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|
|
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system.cpu.dcache.demand_hits 26491207 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 26491207 # number of overall hits
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|
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system.cpu.dcache.ReadReq_misses 552 # number of ReadReq misses
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|
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system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses
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|
|
|
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system.cpu.dcache.demand_misses 6094 # number of demand (read+write) misses
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|
|
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system.cpu.dcache.overall_misses 6094 # number of overall misses
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|
|
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system.cpu.dcache.ReadReq_miss_latency 28390000 # number of ReadReq miss cycles
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|
|
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system.cpu.dcache.WriteReq_miss_latency 303795000 # number of WriteReq miss cycles
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|
|
|
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system.cpu.dcache.demand_miss_latency 332185000 # number of demand (read+write) miss cycles
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|
|
|
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system.cpu.dcache.overall_miss_latency 332185000 # number of overall miss cycles
|
2009-05-12 21:01:16 +02:00
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|
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system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
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|
|
|
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system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
2011-06-20 03:43:42 +02:00
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|
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system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses
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|
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system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 51431.159420 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 54816.853122 # average WriteReq miss latency
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|
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system.cpu.dcache.demand_avg_miss_latency 54510.173942 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 54510.173942 # average overall miss latency
|
2009-05-12 21:01:16 +02:00
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|
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-06-20 03:43:42 +02:00
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|
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system.cpu.dcache.blocked_cycles::no_targets 41040500 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked
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|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 49866.950182 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.writebacks 107 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 77 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 3871 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 3871 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 92992000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 116205000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 116205000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53199.084668 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 2189.147121 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 6359 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 3281 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 1.938129 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 2171.310088 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 17.837033 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.066263 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 6350 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.demand_hits 6376 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 6376 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 3215 # number of ReadReq misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.demand_misses 4937 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 4937 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 168259500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 90562500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 258822000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 258822000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 9565 # number of ReadReq accesses(hits+misses)
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 11313 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 11313 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.336121 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.436401 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.436401 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52335.769829 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52591.463415 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52424.954426 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52424.954426 # average overall miss latency
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3215 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 4937 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 4937 # number of overall MSHR misses
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 129008000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 198352500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 198352500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.336121 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.436401 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.436401 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40126.905132 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.744483 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2009-05-12 21:01:16 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2009-05-12 21:01:16 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
