sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

1555 lines
178 KiB
Plaintext
Raw Normal View History

ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
sim_seconds 2.572328 # Number of seconds simulated
sim_ticks 2572328372500 # Number of ticks simulated
final_tick 2572328372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
host_inst_rate 81734 # Simulator instruction rate (inst/s)
host_op_rate 105574 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3400147622 # Simulator tick rate (ticks/s)
host_mem_usage 384052 # Number of bytes of host memory used
host_seconds 756.53 # Real time elapsed on the host
sim_insts 61834256 # Number of instructions simulated
sim_ops 79870174 # Number of ops (including micro ops) simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.nvmem.bytes_read 384 # Number of bytes read from this memory
system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
system.nvmem.bytes_written 0 # Number of bytes written to this memory
system.nvmem.num_reads 6 # Number of read requests responded to by this memory
system.nvmem.num_writes 0 # Number of write requests responded to by this memory
system.nvmem.num_other 0 # Number of other requests responded to by this memory
system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.physmem.bytes_read 131402148 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1183168 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10205776 # Number of bytes written to this memory
system.physmem.num_reads 15127689 # Number of read requests responded to by this memory
system.physmem.num_writes 869419 # Number of write requests responded to by this memory
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.physmem.num_other 0 # Number of other requests responded to by this memory
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.physmem.bw_read 51082960 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 459960 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 3967525 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 55050485 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 130931 # number of replacements
system.l2c.tagsinuse 27519.920349 # Cycle average of tags in use
system.l2c.total_refs 1850900 # Total number of references to valid blocks.
system.l2c.sampled_refs 160584 # Sample count of references to valid blocks.
system.l2c.avg_refs 11.526055 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.occ_blocks::writebacks 15169.797230 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 19.693620 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.048154 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 2916.118065 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 1448.517664 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 24.954124 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker 0.021877 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 3298.971983 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 4641.797632 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.231473 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.044496 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.022103 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000381 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.050338 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.070828 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.419921 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 55824 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 5360 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 353946 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 138985 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 116300 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6415 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 686444 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 224154 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1587428 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 602817 # number of Writeback hits
system.l2c.Writeback_hits::total 602817 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 916 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 896 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1812 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 349 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 559 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 36704 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 64640 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 101344 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 55824 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5360 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 353946 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 175689 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 116300 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6415 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 686444 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 288794 # number of demand (read+write) hits
system.l2c.demand_hits::total 1688772 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 55824 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5360 # number of overall hits
system.l2c.overall_hits::cpu0.inst 353946 # number of overall hits
system.l2c.overall_hits::cpu0.data 175689 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 116300 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6415 # number of overall hits
system.l2c.overall_hits::cpu1.inst 686444 # number of overall hits
system.l2c.overall_hits::cpu1.data 288794 # number of overall hits
system.l2c.overall_hits::total 1688772 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 75 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 9410 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 9224 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 52 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 6 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 8908 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 12134 # number of ReadReq misses
system.l2c.ReadReq_misses::total 39813 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 5335 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 5536 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 10871 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 765 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 529 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1294 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 66271 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 81270 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 147541 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 75 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 9410 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 75495 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 52 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 6 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 8908 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 93404 # number of demand (read+write) misses
system.l2c.demand_misses::total 187354 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 75 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.inst 9410 # number of overall misses
system.l2c.overall_misses::cpu0.data 75495 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 52 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 6 # number of overall misses
system.l2c.overall_misses::cpu1.inst 8908 # number of overall misses
system.l2c.overall_misses::cpu1.data 93404 # number of overall misses
system.l2c.overall_misses::total 187354 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3910000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 210000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 492070500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 481346500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2708500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 312500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 465974500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 633905500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2080438000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 18240000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 37260500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 55500500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2038000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5120000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 7158000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3474892499 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4269418500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7744310999 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 3910000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 210000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 492070500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3956238999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 2708500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 312500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 465974500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4903324000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 9824748999 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 3910000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 210000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 492070500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3956238999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 2708500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 312500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 465974500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4903324000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 9824748999 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 55899 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 5364 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 363356 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 148209 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 116352 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6421 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 695352 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 236288 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1627241 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 602817 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 602817 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 6251 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 6432 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 12683 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 878 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1853 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 102975 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 145910 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 248885 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 55899 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 5364 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 363356 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 251184 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 116352 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6421 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 695352 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 382198 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1876126 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 55899 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 5364 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 363356 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 251184 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 116352 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6421 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 695352 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 382198 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1876126 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000746 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.025897 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.062236 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000934 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.012811 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.051353 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.853463 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.860697 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784615 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.602506 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.643564 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.556987 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000746 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.025897 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.300557 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000934 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.012811 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.244386 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000746 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.025897 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.300557 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000934 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.012811 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.244386 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52292.295430 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.139202 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average ReadReq miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52083.333333 # average ReadReq miss latency
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52309.665469 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52242.088347 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3418.931584 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6730.581647 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2664.052288 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9678.638941 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52434.586757 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52533.757844 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52292.295430 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52403.987006 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average overall miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.demand_avg_miss_latency::cpu1.inst 52309.665469 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52495.867415 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52292.295430 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52403.987006 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average overall miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.overall_avg_miss_latency::cpu1.inst 52309.665469 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52495.867415 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.writebacks::writebacks 112135 # number of writebacks
system.l2c.writebacks::total 112135 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 52 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 14 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 33 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 52 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 33 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 52 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 33 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 102 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 75 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 9408 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 9172 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 51 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 8894 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 12101 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 39711 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5335 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 5536 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 10871 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 765 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 529 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1294 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 66271 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 81270 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 147541 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 75 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 9408 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 75443 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 51 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 6 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 8894 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 93371 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 187252 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 75 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 9408 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 75443 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 51 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 6 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 8894 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 93371 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 187252 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 162000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 377008500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 367415500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 240000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356843500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 484732500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1591450000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213651500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 221567500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 435219000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30631000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21186500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 51817500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2653011999 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3258908000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5911919999 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 162000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 377008500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 3020427499 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 240000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 356843500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3743640500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 7503369999 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 162000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 377008500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 3020427499 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 240000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 356843500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3743640500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 7503369999 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5748500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468870500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493886000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131970436000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744869980 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777552693 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 32522422673 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213740480 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271438693 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 164492858673 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061886 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051213 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853463 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860697 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784615 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602506 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643564 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556987 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40058.384213 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.226675 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.141518 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.031069 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.522876 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.094518 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.774502 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40099.766211 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dtb.read_hits 7800657 # DTB read hits
system.cpu0.dtb.read_misses 37871 # DTB read misses
system.cpu0.dtb.write_hits 4594363 # DTB write hits
system.cpu0.dtb.write_misses 6405 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 4617 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dtb.perms_faults 804 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7838528 # DTB read accesses
system.cpu0.dtb.write_accesses 4600768 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dtb.hits 12395020 # DTB hits
system.cpu0.dtb.misses 44276 # DTB misses
system.cpu0.dtb.accesses 12439296 # DTB accesses
system.cpu0.itb.inst_hits 4047811 # ITB inst hits
system.cpu0.itb.inst_misses 4513 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.itb.perms_faults 1822 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.itb.inst_accesses 4052324 # ITB inst accesses
system.cpu0.itb.hits 4047811 # DTB hits
system.cpu0.itb.misses 4513 # DTB misses
system.cpu0.itb.accesses 4052324 # DTB accesses
system.cpu0.numCycles 58217040 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.BPredUnit.lookups 5494906 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 4166450 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 326433 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 3744504 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 2784648 # Number of BTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.BPredUnit.usedRAS 487236 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 65325 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 11075516 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 28672475 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 5494906 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 3271884 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 6845901 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1471988 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 58967 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 18678527 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 6609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 30991 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 80316 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 4045687 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 176720 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3125 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 37812790 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.988034 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.366493 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.fetch.rateDist::0 30973406 81.91% 81.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 543248 1.44% 83.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 812383 2.15% 85.50% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 623093 1.65% 87.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 608176 1.61% 88.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 518047 1.37% 90.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 610247 1.61% 91.74% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 354921 0.94% 92.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2769269 7.32% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.fetch.rateDist::total 37812790 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.094387 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.492510 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 11408065 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 18778956 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 6151939 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 496838 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 976992 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 873407 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 60147 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 35984632 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 191719 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 976992 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 11949753 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 4623091 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 12461431 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 6096265 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 1705258 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 34697309 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 704 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 354137 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 881144 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 56 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 34828806 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 157685767 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 157645150 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 40617 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 26885345 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 7943461 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 453210 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 414972 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 4454682 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 6732960 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5163615 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 859688 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 866427 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 32711333 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 727944 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 32879139 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 79039 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 5868829 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 13573267 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 126473 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 37812790 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.869524 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.504625 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iq.issued_per_cycle::0 24425873 64.60% 64.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 5253388 13.89% 78.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 2719158 7.19% 85.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2012461 5.32% 91.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1865520 4.93% 95.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 793449 2.10% 98.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 530235 1.40% 99.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 162331 0.43% 99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 50375 0.13% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iq.issued_per_cycle::total 37812790 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iq.fu_full::IntAlu 17246 1.80% 1.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 470 0.05% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 745499 77.99% 79.84% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 192658 20.16% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 19663366 59.80% 59.85% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 43374 0.13% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 5 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.98% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 8245355 25.08% 85.06% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 4911741 14.94% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iq.FU_type_0::total 32879139 # Type of FU issued
system.cpu0.iq.rate 0.564768 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 955873 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.029072 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 104638650 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 39311978 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 30147071 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 10735 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 5504 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 4409 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 33814871 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 5860 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 258705 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 1302867 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 9804 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 555393 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 1948839 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 5274 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iew.iewSquashCycles 976992 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 3526747 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 77009 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 33493958 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 132151 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 6732960 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5163615 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 457776 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 36292 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 4432 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 9804 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 205792 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 118466 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 324258 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 32446755 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 8074532 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 432384 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iew.exec_nop 54681 # number of nop insts executed
system.cpu0.iew.exec_refs 12932399 # number of memory reference insts executed
system.cpu0.iew.exec_branches 4282280 # Number of branches executed
system.cpu0.iew.exec_stores 4857867 # Number of stores executed
system.cpu0.iew.exec_rate 0.557341 # Inst execution rate
system.cpu0.iew.wb_sent 32234818 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 30151480 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 16076835 # num instructions producing a value
system.cpu0.iew.wb_consumers 31416355 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.iew.wb_rate 0.517915 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.511735 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.commit.commitCommittedInsts 20629504 # The number of committed instructions
system.cpu0.commit.commitCommittedOps 27347391 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 5995379 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 601471 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 285121 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 36866578 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.741794 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.700144 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.commit.committed_per_cycle::0 26502705 71.89% 71.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 5217604 14.15% 86.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 1684301 4.57% 90.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 813710 2.21% 92.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 652862 1.77% 94.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 391356 1.06% 95.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 444768 1.21% 96.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 190957 0.52% 97.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 968315 2.63% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.commit.committed_per_cycle::total 36866578 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 20629504 # Number of instructions committed
system.cpu0.commit.committedOps 27347391 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.commit.refs 10038315 # Number of memory references committed
system.cpu0.commit.loads 5430093 # Number of loads committed
system.cpu0.commit.membars 201113 # Number of memory barriers committed
system.cpu0.commit.branches 3777887 # Number of branches committed
system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 24270652 # Number of committed integer instructions.
system.cpu0.commit.function_calls 441072 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 968315 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.rob.rob_reads 68594693 # The number of ROB reads
system.cpu0.rob.rob_writes 67665332 # The number of ROB writes
system.cpu0.timesIdled 379309 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 20404250 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5085681345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 20604950 # Number of Instructions Simulated
system.cpu0.committedOps 27322837 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 20604950 # Number of Instructions Simulated
system.cpu0.cpi 2.825391 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.825391 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.353933 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.353933 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 151241601 # number of integer regfile reads
system.cpu0.int_regfile_writes 29619273 # number of integer regfile writes
system.cpu0.fp_regfile_reads 4540 # number of floating regfile reads
system.cpu0.fp_regfile_writes 420 # number of floating regfile writes
system.cpu0.misc_regfile_reads 40596238 # number of misc regfile reads
system.cpu0.misc_regfile_writes 457019 # number of misc regfile writes
system.cpu0.icache.replacements 364224 # number of replacements
system.cpu0.icache.tagsinuse 511.052791 # Cycle average of tags in use
system.cpu0.icache.total_refs 3649617 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 364736 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 10.006188 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 511.052791 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 3649617 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 3649617 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 3649617 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 3649617 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 3649617 # number of overall hits
system.cpu0.icache.overall_hits::total 3649617 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 395923 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 395923 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 395923 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 395923 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 395923 # number of overall misses
system.cpu0.icache.overall_misses::total 395923 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6038304987 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6038304987 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6038304987 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6038304987 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6038304987 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6038304987 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4045540 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 4045540 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 4045540 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 4045540 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 4045540 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 4045540 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097867 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097867 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097867 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.210430 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1459990 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 7411.116751 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.icache.writebacks::writebacks 18468 # number of writebacks
system.cpu0.icache.writebacks::total 18468 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31062 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 31062 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 31062 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 31062 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 31062 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 31062 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 364861 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 364861 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 364861 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 364861 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 364861 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 364861 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4524888490 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4524888490 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4524888490 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4524888490 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4524888490 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4524888490 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7723000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7723000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7723000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7723000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dcache.replacements 240566 # number of replacements
system.cpu0.dcache.tagsinuse 465.688994 # Cycle average of tags in use
system.cpu0.dcache.total_refs 8072207 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 240949 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 33.501724 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 49733000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 465.688994 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.909549 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.909549 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5008601 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5008601 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 2710702 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 2710702 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 158809 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 158809 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 156314 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 156314 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7719303 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 7719303 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7719303 # number of overall hits
system.cpu0.dcache.overall_hits::total 7719303 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 337108 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 337108 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1466456 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1466456 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8650 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 8650 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7736 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7736 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1803564 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1803564 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1803564 # number of overall misses
system.cpu0.dcache.overall_misses::total 1803564 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4776619000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 4776619000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60194469903 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 60194469903 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98955000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 98955000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83321000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 83321000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 64971088903 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 64971088903 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 64971088903 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 64971088903 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5345709 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 5345709 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177158 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4177158 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167459 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 167459 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164050 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 164050 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 9522867 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 9522867 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 9522867 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 9522867 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063061 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351065 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051654 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047156 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189393 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189393 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14169.402684 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41047.579950 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11439.884393 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10770.553257 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 4293490 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 2319000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 358 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 107 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11992.988827 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 21672.897196 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dcache.writebacks::writebacks 213312 # number of writebacks
system.cpu0.dcache.writebacks::total 213312 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173688 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 173688 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346623 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1346623 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1520311 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1520311 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1520311 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1520311 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163420 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 163420 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119833 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 119833 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8036 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8036 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 283253 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 283253 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 283253 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 283253 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2117873500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2117873500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4308779989 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4308779989 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66427000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66427000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60070500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60070500 # number of StoreCondReq MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426653489 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 6426653489 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426653489 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 6426653489 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482117000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482117000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884866891 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884866891 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366983891 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366983891 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030570 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028688 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047988 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047150 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12959.695876 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35956.539426 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8266.177203 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7766.063348 # average StoreCondReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.dtb.read_hits 44928224 # DTB read hits
system.cpu1.dtb.read_misses 73602 # DTB read misses
system.cpu1.dtb.write_hits 7780505 # DTB write hits
system.cpu1.dtb.write_misses 20150 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.dtb.flush_entries 2631 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 7056 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 592 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.dtb.perms_faults 1808 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 45001826 # DTB read accesses
system.cpu1.dtb.write_accesses 7800655 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.dtb.hits 52708729 # DTB hits
system.cpu1.dtb.misses 93752 # DTB misses
system.cpu1.dtb.accesses 52802481 # DTB accesses
system.cpu1.itb.inst_hits 10224529 # ITB inst hits
system.cpu1.itb.inst_misses 7346 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.itb.flush_entries 1545 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.itb.perms_faults 4985 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.itb.inst_accesses 10231875 # ITB inst accesses
system.cpu1.itb.hits 10224529 # DTB hits
system.cpu1.itb.misses 7346 # DTB misses
system.cpu1.itb.accesses 10231875 # DTB accesses
system.cpu1.numCycles 361675233 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.BPredUnit.lookups 10827639 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 8483405 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 651414 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 7693556 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 6128118 # Number of BTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.BPredUnit.usedRAS 880194 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 140008 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 23684849 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 77430542 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 10827639 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 7008312 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 16767403 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 5372389 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 95383 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 76264591 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5418 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 105344 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 159017 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 10219281 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 840043 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3905 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 120738841 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.782294 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.150601 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.fetch.rateDist::0 103983967 86.12% 86.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 1000458 0.83% 86.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 1336299 1.11% 88.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 2219256 1.84% 89.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1499731 1.24% 91.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 782401 0.65% 91.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 2303716 1.91% 93.69% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 514923 0.43% 94.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 7098090 5.88% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.fetch.rateDist::total 120738841 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.029937 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.214089 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 25308158 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 76213029 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 15039933 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 636285 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 3541436 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1506236 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 117566 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 87857465 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 382082 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 3541436 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 26899042 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 32453857 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 39247498 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 14094152 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 4502856 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 81303435 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 2397 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 630313 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 3163900 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 46270 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 85880003 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 375960450 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 375911455 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 48995 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 53654703 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 32225299 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 777903 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 702371 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 8742657 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 15637648 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 9415892 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 1206366 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1577382 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 72765269 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1195198 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 96700645 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 136833 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 20828043 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 58949605 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 235739 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 120738841 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.800908 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.525223 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iq.issued_per_cycle::0 86966093 72.03% 72.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 10006677 8.29% 80.32% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 4983433 4.13% 84.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 4114228 3.41% 87.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 11017570 9.13% 96.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 2069642 1.71% 98.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1195614 0.99% 99.68% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 292428 0.24% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 93156 0.08% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iq.issued_per_cycle::total 120738841 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iq.fu_full::IntAlu 40933 0.51% 0.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 999 0.01% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 7708137 95.31% 95.83% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 337009 4.17% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 92785 0.10% 0.10% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 42154384 43.59% 43.69% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 68643 0.07% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 27 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 32 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1443 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.76% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 46199078 47.78% 91.54% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 8184247 8.46% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iq.FU_type_0::total 96700645 # Type of FU issued
system.cpu1.iq.rate 0.267369 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 8087078 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.083630 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 322445450 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 94804325 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 60018746 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 12063 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 6724 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 104688665 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 6273 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 377137 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 4715368 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 6098 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 23303 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1781253 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 32175806 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 1149693 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iew.iewSquashCycles 3541436 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 25051723 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 357920 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 74130311 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 221482 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 15637648 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 9415892 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 813116 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 58494 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 8530 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 23303 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 417083 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 225221 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 642304 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 93796024 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 45359703 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 2904621 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iew.exec_nop 169844 # number of nop insts executed
system.cpu1.iew.exec_refs 53443268 # number of memory reference insts executed
system.cpu1.iew.exec_branches 7814764 # Number of branches executed
system.cpu1.iew.exec_stores 8083565 # Number of stores executed
system.cpu1.iew.exec_rate 0.259338 # Inst execution rate
system.cpu1.iew.wb_sent 92469231 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 60024243 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 32803499 # num instructions producing a value
system.cpu1.iew.wb_consumers 59096106 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.iew.wb_rate 0.165962 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.555087 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.commit.commitCommittedInsts 41355133 # The number of committed instructions
system.cpu1.commit.commitCommittedOps 52673164 # The number of committed instructions
system.cpu1.commit.commitSquashedInsts 21398329 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 959459 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 564799 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 117251310 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.449233 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.403225 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.commit.committed_per_cycle::0 98126146 83.69% 83.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 9730536 8.30% 91.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 2573774 2.20% 94.18% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1441495 1.23% 95.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1191073 1.02% 96.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 709985 0.61% 97.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 1084141 0.92% 97.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 501748 0.43% 98.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1892412 1.61% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.commit.committed_per_cycle::total 117251310 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 41355133 # Number of instructions committed
system.cpu1.commit.committedOps 52673164 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.commit.refs 18556919 # Number of memory references committed
system.cpu1.commit.loads 10922280 # Number of loads committed
system.cpu1.commit.membars 235767 # Number of memory barriers committed
system.cpu1.commit.branches 6572492 # Number of branches committed
system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 46935651 # Number of committed integer instructions.
system.cpu1.commit.function_calls 612387 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1892412 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.rob.rob_reads 188242511 # The number of ROB reads
system.cpu1.rob.rob_writes 151809339 # The number of ROB writes
system.cpu1.timesIdled 1543775 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 240936392 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 4782922080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 41229306 # Number of Instructions Simulated
system.cpu1.committedOps 52547337 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 41229306 # Number of Instructions Simulated
system.cpu1.cpi 8.772285 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 8.772285 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.113995 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.113995 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 421917398 # number of integer regfile reads
system.cpu1.int_regfile_writes 62840714 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4256 # number of floating regfile reads
system.cpu1.fp_regfile_writes 1992 # number of floating regfile writes
system.cpu1.misc_regfile_reads 99685734 # number of misc regfile reads
system.cpu1.misc_regfile_writes 498572 # number of misc regfile writes
system.cpu1.icache.replacements 696666 # number of replacements
system.cpu1.icache.tagsinuse 498.774287 # Cycle average of tags in use
system.cpu1.icache.total_refs 9464320 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 697178 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 13.575185 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 74291126000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 498.774287 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.974169 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.974169 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 9464320 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 9464320 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 9464320 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 9464320 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 9464320 # number of overall hits
system.cpu1.icache.overall_hits::total 9464320 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 754908 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 754908 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 754908 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 754908 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 754908 # number of overall misses
system.cpu1.icache.overall_misses::total 754908 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11029274493 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 11029274493 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 11029274493 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 11029274493 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 11029274493 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 11029274493 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 10219228 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 10219228 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 10219228 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 10219228 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 10219228 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 10219228 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073871 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073871 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073871 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14610.090889 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 1452995 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.icache.blocked::no_mshrs 231 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 6290.021645 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.icache.writebacks::writebacks 33177 # number of writebacks
system.cpu1.icache.writebacks::total 33177 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57704 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 57704 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 57704 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 57704 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 57704 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 57704 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 697204 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 697204 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 697204 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 697204 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 697204 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 697204 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8247682495 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8247682495 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8247682495 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 8247682495 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8247682495 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 8247682495 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.dcache.replacements 407468 # number of replacements
system.cpu1.dcache.tagsinuse 452.466365 # Cycle average of tags in use
system.cpu1.dcache.total_refs 14808453 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 407980 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 36.297007 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 72560362000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 452.466365 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.883723 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.883723 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 9771721 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 9771721 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4750886 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4750886 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123631 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 123631 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 116540 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 116540 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 14522607 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 14522607 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 14522607 # number of overall hits
system.cpu1.dcache.overall_hits::total 14522607 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 451897 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 451897 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1700738 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1700738 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14109 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 14109 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10120 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10120 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 2152635 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 2152635 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 2152635 # number of overall misses
system.cpu1.dcache.overall_misses::total 2152635 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6794357500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 6794357500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56737247402 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 56737247402 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 169367000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 169367000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 85782500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 85782500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 63531604902 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 63531604902 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 63531604902 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 63531604902 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 10223618 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 10223618 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6451624 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 6451624 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137740 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 137740 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 126660 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 126660 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 16675242 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 16675242 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 16675242 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 16675242 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044201 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263614 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102432 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079899 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129092 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129092 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15035.190541 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33360.369088 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12004.181728 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8476.531621 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 14045059 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 5012000 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 3121 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 132 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4500.179109 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 37969.696970 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.dcache.writebacks::writebacks 337861 # number of writebacks
system.cpu1.dcache.writebacks::total 337861 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 189374 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 189374 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1526129 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 1526129 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1128 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1128 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1715503 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1715503 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1715503 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1715503 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262523 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 262523 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174609 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 174609 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12981 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12981 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10116 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10116 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 437132 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 437132 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 437132 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 437132 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3281013000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3281013000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5495017558 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5495017558 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 116690000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 116690000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55378500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55378500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8776030558 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 8776030558 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8776030558 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 8776030558 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933382500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933382500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618386548 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618386548 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551769048 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551769048 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025678 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094243 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079867 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12498.002080 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31470.414228 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8989.292042 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5474.347568 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1308182536142 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1308182536142 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu0.kern.inst.quiesce 38025 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu1.kern.inst.quiesce 59433 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink