2008-09-28 23:15:50 +02:00
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---------- Begin Simulation Statistics ----------
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2010-02-25 19:08:41 +01:00
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host_inst_rate 178423 # Simulator instruction rate (inst/s)
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host_mem_usage 199584 # Number of bytes of host memory used
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host_seconds 10217.56 # Real time elapsed on the host
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host_tick_rate 69014447 # Simulator tick rate (ticks/s)
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2008-09-28 23:15:50 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1823043370 # Number of instructions simulated
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sim_seconds 0.705159 # Number of seconds simulated
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sim_ticks 705159454500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 240462096 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 294213603 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 349424731 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target.
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2008-09-28 23:15:50 +02:00
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system.cpu.commit.COM:branches 266706457 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2009-04-22 19:25:17 +02:00
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system.cpu.commit.COM:committed_per_cycle::samples 1310002801 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.533575 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.199105 # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0-1 603585597 46.08% 46.08% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1-2 273587005 20.88% 66.96% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2-3 174037133 13.29% 80.24% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3-4 65399708 4.99% 85.24% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4-5 48333001 3.69% 88.93% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5-6 34003110 2.60% 91.52% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6-7 18481318 1.41% 92.93% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7-8 23715685 1.81% 94.74% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 68860244 5.26% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 1310002801 # Number of insts commited each cycle
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2008-09-28 23:15:50 +02:00
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system.cpu.commit.COM:count 2008987604 # Number of instructions committed
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system.cpu.commit.COM:loads 511595302 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 722390433 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
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2008-12-05 18:09:29 +01:00
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system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit
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2008-09-28 23:15:50 +02:00
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system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
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system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 5124.928571 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 18000 # average number of cycles each access was blocked
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks.
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 143498 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2010-02-25 19:08:41 +01:00
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system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4095.104513 # Average occupied blocks per context
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.overall_hits 674038251 # number of overall hits
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system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.overall_misses 2493914 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1526847 # number of replacements
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system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use
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2008-12-05 18:09:29 +01:00
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system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks.
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 74589 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch
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2008-12-05 18:09:29 +01:00
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system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running
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2008-09-28 23:15:50 +02:00
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system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.data_accesses 775959987 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 775335043 # DTB hits
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system.cpu.dtb.data_misses 624944 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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2008-12-05 18:09:29 +01:00
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system.cpu.dtb.read_accesses 516992085 # DTB read accesses
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2008-09-28 23:15:50 +02:00
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system.cpu.dtb.read_acv 0 # DTB read access violations
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2008-12-05 18:09:29 +01:00
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system.cpu.dtb.read_hits 516404963 # DTB read hits
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2008-09-28 23:15:50 +02:00
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system.cpu.dtb.read_misses 587122 # DTB read misses
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2008-12-05 18:09:29 +01:00
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system.cpu.dtb.write_accesses 258967902 # DTB write accesses
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2008-09-28 23:15:50 +02:00
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system.cpu.dtb.write_acv 0 # DTB write access violations
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2008-12-05 18:09:29 +01:00
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system.cpu.dtb.write_hits 258930080 # DTB write hits
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2008-09-28 23:15:50 +02:00
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system.cpu.dtb.write_misses 37822 # DTB write misses
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2008-12-05 18:09:29 +01:00
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system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered
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2008-09-28 23:15:50 +02:00
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system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched
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system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed
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2008-12-05 18:09:29 +01:00
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system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed
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2009-04-15 22:13:58 +02:00
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system.cpu.fetch.SquashCycles 29544621 # Number of cycles fetch has spent squashing
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2008-09-28 23:15:50 +02:00
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system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss
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2008-12-05 18:09:29 +01:00
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system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken
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2008-09-28 23:15:50 +02:00
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system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle
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2009-04-22 19:25:17 +02:00
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system.cpu.fetch.rateDist::samples 1410161885 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.148845 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.029305 # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0-1 830588040 58.90% 58.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1-2 53463106 3.79% 62.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2-3 39766072 2.82% 65.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3-4 63538024 4.51% 70.02% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4-5 121390719 8.61% 78.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5-6 35256321 2.50% 81.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6-7 38761682 2.75% 83.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7-8 6988644 0.50% 84.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 220409277 15.63% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1410161885 # Number of instructions fetched each cycle (Total)
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2008-09-28 23:15:50 +02:00
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system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits
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|
system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.icache.occ_%::0 0.788136 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 1614.102824 # Average occupied blocks per context
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.overall_hits 348437250 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 10649 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 8097 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.EXEC:branches 274534145 # Number of branches executed
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 258968900 # Number of stores executed
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.WB:producers 1136229268 # num instructions producing a value
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1204412678 57.64% 57.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% 57.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851349 1.33% 58.97% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254694 0.40% 59.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.34% 59.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 557993260 26.70% 86.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283770831 13.58% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 2089507805 # Type of FU issued
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 8291 0.02% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 28032977 75.57% 75.60% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 9052278 24.40% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 1410161885 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.481750 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637343 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 537278436 38.10% 38.10% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 285217724 20.23% 58.33% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 273546804 19.40% 77.72% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 154810620 10.98% 88.70% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 63341841 4.49% 93.19% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 51438515 3.65% 96.84% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 32491109 2.30% 99.15% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 9036668 0.64% 99.79% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 3000168 0.21% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 1410161885 # Number of insts issued each cycle
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.fetch_accesses 348448092 # ITB accesses
|
|
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.itb.fetch_hits 348447899 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 193 # ITB misses
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8187.500000 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 65500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.l2cache.occ_%::0 0.927694 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.046416 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 30398.691034 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 1520.954518 # Average occupied blocks per context
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.overall_hits 28934 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 1511777 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 1474251 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 66899 # number of writebacks
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.memDep0.conflictingLoads 118847053 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 21034746 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 303651290 # Number of stores inserted to the mem dependence unit.
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.numCycles 1410318910 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
