2008-09-28 23:15:50 +02:00
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---------- Begin Simulation Statistics ----------
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2010-05-14 05:45:59 +02:00
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host_inst_rate 173583 # Simulator instruction rate (inst/s)
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host_mem_usage 213764 # Number of bytes of host memory used
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host_seconds 10502.41 # Real time elapsed on the host
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host_tick_rate 66694888 # Simulator tick rate (ticks/s)
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2008-09-28 23:15:50 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1823043370 # Number of instructions simulated
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2010-05-14 05:45:59 +02:00
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sim_seconds 0.700457 # Number of seconds simulated
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sim_ticks 700456762500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2010-05-14 05:45:59 +02:00
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system.cpu.BPredUnit.BTBHits 237313176 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 290294551 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 3578 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 28357853 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 231827098 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 346133867 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 49328779 # Number of times the RAS was used to get a target.
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2008-09-28 23:15:50 +02:00
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system.cpu.commit.COM:branches 266706457 # Number of branches committed
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.COM:bw_lim_events 69311011 # number cycles where commit BW limit reached
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2008-09-28 23:15:50 +02:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.COM:committed_per_cycle::samples 1302157693 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.542814 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.203929 # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.COM:committed_per_cycle::0-1 596380613 45.80% 45.80% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1-2 273242120 20.98% 66.78% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2-3 173533589 13.33% 80.11% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3-4 65306568 5.02% 85.13% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4-5 48690140 3.74% 88.86% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5-6 33944722 2.61% 91.47% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6-7 18456166 1.42% 92.89% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7-8 23292764 1.79% 94.68% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 69311011 5.32% 100.00% # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.COM:committed_per_cycle::total 1302157693 # Number of insts commited each cycle
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2008-09-28 23:15:50 +02:00
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system.cpu.commit.COM:count 2008987604 # Number of instructions committed
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system.cpu.commit.COM:loads 511595302 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 722390433 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.branchMispredicts 28346017 # The number of times a branch was mispredicted
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2008-09-28 23:15:50 +02:00
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system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.commitSquashedInsts 686852992 # The number of squashed insts skipped by commit
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2008-09-28 23:15:50 +02:00
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system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
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2010-05-14 05:45:59 +02:00
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system.cpu.cpi 0.768448 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.768448 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 463363512 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 37524.078898 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34794.219854 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 461428955 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 72592469500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.004175 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 475286 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 50774196000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1459271 # number of ReadReq MSHR misses
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 38582.382670 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36523.414699 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 210235446 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 21584913985 # number of WriteReq miss cycles
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_misses 559450 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 484668 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2731293998 # number of WriteReq MSHR miss cycles
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_mshr_misses 74782 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 4879.241379 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 438.740100 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 141498 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.demand_accesses 674158408 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 37761.475202 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 671664401 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 94177383485 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.003699 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2494007 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 959954 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 53505489998 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.002276 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1534053 # number of demand (read+write) MSHR misses
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.occ_%::0 0.999780 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4095.099733 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 674158408 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 37761.475202 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.overall_hits 671664401 # number of overall hits
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system.cpu.dcache.overall_miss_latency 94177383485 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.003699 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2494007 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 959954 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 53505489998 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.002276 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1534053 # number of overall MSHR misses
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.replacements 1526826 # number of replacements
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system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks.
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.tagsinuse 4095.099733 # Cycle average of tags in use
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system.cpu.dcache.total_refs 671676872 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 274383000 # Cycle when the warmup percentage was hit.
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2008-09-28 23:15:50 +02:00
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system.cpu.dcache.writebacks 74589 # number of writebacks
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2010-05-14 05:45:59 +02:00
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system.cpu.decode.DECODE:BlockedCycles 32140341 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 12074 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 30417175 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 2923062124 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 711773443 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 558159581 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 98598096 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 45812 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 84328 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 772918649 # DTB accesses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.data_acv 0 # DTB access violations
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2010-05-14 05:45:59 +02:00
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system.cpu.dtb.data_hits 772293170 # DTB hits
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system.cpu.dtb.data_misses 625479 # DTB misses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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2010-05-14 05:45:59 +02:00
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system.cpu.dtb.read_accesses 514591069 # DTB read accesses
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2008-09-28 23:15:50 +02:00
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system.cpu.dtb.read_acv 0 # DTB read access violations
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2010-05-14 05:45:59 +02:00
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system.cpu.dtb.read_hits 514003488 # DTB read hits
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system.cpu.dtb.read_misses 587581 # DTB read misses
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system.cpu.dtb.write_accesses 258327580 # DTB write accesses
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2008-09-28 23:15:50 +02:00
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system.cpu.dtb.write_acv 0 # DTB write access violations
|
2010-05-14 05:45:59 +02:00
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|
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system.cpu.dtb.write_hits 258289682 # DTB write hits
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|
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system.cpu.dtb.write_misses 37898 # DTB write misses
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system.cpu.fetch.Branches 346133867 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 346369631 # Number of cache lines fetched
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system.cpu.fetch.Cycles 922290632 # Number of cycles fetch has run and was not squashing or blocked
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|
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system.cpu.fetch.IcacheSquashes 4326238 # Number of outstanding Icache misses that were squashed
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|
|
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system.cpu.fetch.Insts 3015904698 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 28794725 # Number of cycles fetch has spent squashing
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|
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system.cpu.fetch.branchRate 0.247077 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 346369631 # Number of cycles fetch is stalled on an Icache miss
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|
|
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system.cpu.fetch.predictedBranches 286641955 # Number of branches that fetch has predicted taken
|
|
|
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system.cpu.fetch.rate 2.152813 # Number of inst fetches per cycle
|
|
|
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system.cpu.fetch.rateDist::samples 1400755789 # Number of instructions fetched each cycle (Total)
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|
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system.cpu.fetch.rateDist::mean 2.153055 # Number of instructions fetched each cycle (Total)
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|
|
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system.cpu.fetch.rateDist::stdev 3.032526 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
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|
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
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|
|
system.cpu.fetch.rateDist::0-1 824834992 58.88% 58.88% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1-2 53206817 3.80% 62.68% # Number of instructions fetched each cycle (Total)
|
|
|
|
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system.cpu.fetch.rateDist::2-3 38924738 2.78% 65.46% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3-4 62366133 4.45% 69.91% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4-5 120532729 8.60% 78.52% # Number of instructions fetched each cycle (Total)
|
|
|
|
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system.cpu.fetch.rateDist::5-6 35808657 2.56% 81.08% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6-7 38526871 2.75% 83.83% # Number of instructions fetched each cycle (Total)
|
|
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|
|
system.cpu.fetch.rateDist::7-8 7024237 0.50% 84.33% # Number of instructions fetched each cycle (Total)
|
|
|
|
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system.cpu.fetch.rateDist::8 219530615 15.67% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
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|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.rateDist::total 1400755789 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 346369631 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 15843.963981 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11642.396973 # average ReadReq mshr miss latency
|
|
|
|
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system.cpu.icache.ReadReq_hits 346358970 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 168912500 # number of ReadReq miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.ReadReq_misses 10661 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 882 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 113851000 # number of ReadReq MSHR miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 9779 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.avg_refs 35418.649146 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_accesses 346369631 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 15843.963981 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 346358970 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 168912500 # number of demand (read+write) miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_misses 10661 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 882 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 113851000 # number of demand (read+write) MSHR miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 9779 # number of demand (read+write) MSHR misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.788131 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 1614.092315 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 346369631 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 15843.963981 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_hits 346358970 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 168912500 # number of overall miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_misses 10661 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 882 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 113851000 # number of overall MSHR miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 9779 # number of overall MSHR misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.replacements 8106 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks.
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.tagsinuse 1614.092315 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 346358970 # Total number of references to valid blocks.
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.idleCycles 157737 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 273840918 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 328413541 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.427157 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 773454371 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 258328581 # Number of stores executed
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:consumers 1628963056 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 1998305294 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.696273 # average fanout of values written-back
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:producers 1134203072 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.426430 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 1999262446 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 30877558 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 3458881 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 652332333 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 52328 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 302847672 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2706062248 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 515125790 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 84024827 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1999323821 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 131467 # Number of times the IQ has become full, causing a stall
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 2941 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 98598096 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 141241 # Number of cycles IEW is unblocking
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 63 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 50635810 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 214 # Number of memory responses ignored because the instruction is squashed
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 3618 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 4111 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 140737031 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 92052541 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 3618 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 787831 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 30089727 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.301325 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.301325 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1201800948 57.69% 57.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% 57.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851361 1.34% 59.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254692 0.40% 59.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.77% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.77% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.77% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.77% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 555085010 26.64% 86.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283131644 13.59% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 2083348648 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 37044117 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.017781 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 7263 0.02% 0.02% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 27908776 75.34% 75.36% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 9128078 24.64% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 1400755789 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.487303 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636763 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 530170444 37.85% 37.85% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 284246633 20.29% 58.14% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 272843485 19.48% 77.62% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 155156600 11.08% 88.70% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 63055400 4.50% 93.20% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 50914622 3.63% 96.83% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 32393130 2.31% 99.15% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 9012045 0.64% 99.79% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 2963430 0.21% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 1400755789 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.487136 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 2377648640 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 2083348648 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 554578210 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 12403574 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 512095612 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.itb.fetch_accesses 346369835 # ITB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.itb.fetch_hits 346369631 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 204 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 71651 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.884984 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.644583 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2514297000 # number of ReadExReq miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 71651 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297535500 # number of ReadExReq MSHR miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 71651 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1469050 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34290.352977 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.454128 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 28927 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 49382326000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.980309 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 1440123 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 44644467000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980309 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1440123 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 3136 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34061.702806 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.830357 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 106817500 # number of UpgradeReq miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 3136 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97331500 # number of UpgradeReq MSHR miss cycles
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 3136 # number of UpgradeReq MSHR misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6458.333333 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.023460 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 1540701 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34328.294441 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 28927 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 51896623000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.981225 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 1511774 # number of demand (read+write) misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 46942002500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.981225 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 1511774 # number of demand (read+write) MSHR misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.927763 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.046370 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 30400.923469 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 1519.457016 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 1540701 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34328.294441 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_hits 28927 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 51896623000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.981225 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 1511774 # number of overall misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 46942002500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.981225 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 1511774 # number of overall MSHR misses
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.replacements 1474248 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 1506806 # Sample count of references to valid blocks.
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 31920.380484 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 35349 # Total number of references to valid blocks.
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 66899 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 118618588 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 21042992 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 652332333 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 302847672 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 1400913526 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 20115016 # Number of cycles rename is blocking
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 673890 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 725392322 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 11324949 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 3294871470 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 2827359257 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 1880881832 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 543088621 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 98598096 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 13538505 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 495912762 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 23229 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 2930 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 27590681 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 4075 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2008-09-28 23:15:50 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
