gem5/src/cpu/testers/rubytest/Check.cc

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/*
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* Copyright (c) 2009 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
testers: move testers to a new directory This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
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#include "cpu/testers/rubytest/Check.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/RubyTest.hh"
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#include "mem/ruby/common/SubBlock.hh"
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typedef RubyTester::SenderState SenderState;
Check::Check(Addr address, Addr pc, int _num_writers, int _num_readers,
RubyTester* _tester)
: m_num_writers(_num_writers), m_num_readers(_num_readers),
m_tester_ptr(_tester)
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{
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m_status = TesterStatus_Idle;
pickValue();
pickInitiatingNode();
changeAddress(address);
m_pc = pc;
m_access_mode = RubyAccessMode(random_mt.random(0,
RubyAccessMode_NUM - 1));
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m_store_count = 0;
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}
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void
Check::initiate()
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{
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DPRINTF(RubyTest, "initiating\n");
debugPrint();
// currently no protocols support prefetches
if (false && (random_mt.random(0, 0xf) == 0)) {
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initiatePrefetch(); // Prefetch from random processor
}
if (m_tester_ptr->getCheckFlush() && (random_mt.random(0, 0xff) == 0)) {
initiateFlush(); // issue a Flush request from random processor
}
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if (m_status == TesterStatus_Idle) {
initiateAction();
} else if (m_status == TesterStatus_Ready) {
initiateCheck();
} else {
// Pending - do nothing
DPRINTF(RubyTest,
"initiating action/check - failed: action/check is pending\n");
}
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}
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void
Check::initiatePrefetch()
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{
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DPRINTF(RubyTest, "initiating prefetch\n");
int index = random_mt.random(0, m_num_readers - 1);
MasterPort* port = m_tester_ptr->getReadableCpuPort(index);
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Request::Flags flags;
flags.set(Request::PREFETCH);
Packet::Command cmd;
// 1 in 8 chance this will be an exclusive prefetch
if (random_mt.random(0, 0x7) != 0) {
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cmd = MemCmd::ReadReq;
// if necessary, make the request an instruction fetch
if (m_tester_ptr->isInstOnlyCpuPort(index) ||
(m_tester_ptr->isInstDataCpuPort(index) &&
(random_mt.random(0, 0x1)))) {
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flags.set(Request::INST_FETCH);
}
} else {
cmd = MemCmd::WriteReq;
flags.set(Request::PF_EXCLUSIVE);
}
// Prefetches are assumed to be 0 sized
Request *req = new Request(m_address, 0, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
req->setContext(index);
MEM: Remove the Broadcast destination from the packet This patch simplifies the packet by removing the broadcast flag and instead more firmly relying on (and enforcing) the semantics of transactions in the classic memory system, i.e. request packets are routed from a master to a slave based on the address, and when they are created they have neither a valid source, nor destination. On their way to the slave, the request packet is updated with a source field for all modules that multiplex packets from multiple master (e.g. a bus). When a request packet is turned into a response packet (at the final slave), it moves the potentially populated source field to the destination field, and the response packet is routed through any multiplexing components back to the master based on the destination field. Modules that connect multiplexing components, such as caches and bridges store any existing source and destination field in the sender state as a stack (just as before). The packet constructor is simplified in that there is no longer a need to pass the Packet::Broadcast as the destination (this was always the case for the classic memory system). In the case of Ruby, rather than using the parameter to the constructor we now rely on setDest, as there is already another three-argument constructor in the packet class. In many places where the packet information was printed as part of DPRINTFs, request packets would be printed with a numeric "dest" that would always be -1 (Broadcast) and that field is now removed from the printing.
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PacketPtr pkt = new Packet(req, cmd);
// despite the oddity of the 0 size (questionable if this should
// even be allowed), a prefetch is still a read and as such needs
// a place to store the result
uint8_t *data = new uint8_t[1];
pkt->dataDynamic(data);
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// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
pkt->senderState = new SenderState(m_address, req->getSize());
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MEM: Separate requests and responses for timing accesses This patch moves send/recvTiming and send/recvTimingSnoop from the Port base class to the MasterPort and SlavePort, and also splits them into separate member functions for requests and responses: send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, send/recvTimingSnoopResp. A master port sends requests and receives responses, and also receives snoop requests and sends snoop responses. A slave port has the reciprocal behaviour as it receives requests and sends responses, and sends snoop requests and receives snoop responses. For all MemObjects that have only master ports or slave ports (but not both), e.g. a CPU, or a PIO device, this patch merely adds more clarity to what kind of access is taking place. For example, a CPU port used to call sendTiming, and will now call sendTimingReq. Similarly, a response previously came back through recvTiming, which is now recvTimingResp. For the modules that have both master and slave ports, e.g. the bus, the behaviour was previously relying on branches based on pkt->isRequest(), and this is now replaced with a direct call to the apprioriate member function depending on the type of access. Please note that send/recvRetry is still shared by all the timing accessors and remains in the Port base class for now (to maintain the current bus functionality and avoid changing the statistics of all regressions). The packet queue is split into a MasterPort and SlavePort version to facilitate the use of the new timing accessors. All uses of the PacketQueue are updated accordingly. With this patch, the type of packet (request or response) is now well defined for each type of access, and asserts on pkt->isRequest() and pkt->isResponse() are now moved to the appropriate send member functions. It is also worth noting that sendTimingSnoopReq no longer returns a boolean, as the semantics do not alow snoop requests to be rejected or stalled. All these assumptions are now excplicitly part of the port interface itself.
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if (port->sendTimingReq(pkt)) {
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DPRINTF(RubyTest, "successfully initiated prefetch.\n");
} else {
// If the packet did not issue, must delete
delete pkt->senderState;
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delete pkt->req;
delete pkt;
DPRINTF(RubyTest,
"prefetch initiation failed because Port was busy.\n");
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}
}
void
Check::initiateFlush()
{
DPRINTF(RubyTest, "initiating Flush\n");
int index = random_mt.random(0, m_num_writers - 1);
MasterPort* port = m_tester_ptr->getWritableCpuPort(index);
Request::Flags flags;
Request *req = new Request(m_address, CHECK_SIZE, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
Packet::Command cmd;
cmd = MemCmd::FlushReq;
MEM: Remove the Broadcast destination from the packet This patch simplifies the packet by removing the broadcast flag and instead more firmly relying on (and enforcing) the semantics of transactions in the classic memory system, i.e. request packets are routed from a master to a slave based on the address, and when they are created they have neither a valid source, nor destination. On their way to the slave, the request packet is updated with a source field for all modules that multiplex packets from multiple master (e.g. a bus). When a request packet is turned into a response packet (at the final slave), it moves the potentially populated source field to the destination field, and the response packet is routed through any multiplexing components back to the master based on the destination field. Modules that connect multiplexing components, such as caches and bridges store any existing source and destination field in the sender state as a stack (just as before). The packet constructor is simplified in that there is no longer a need to pass the Packet::Broadcast as the destination (this was always the case for the classic memory system). In the case of Ruby, rather than using the parameter to the constructor we now rely on setDest, as there is already another three-argument constructor in the packet class. In many places where the packet information was printed as part of DPRINTFs, request packets would be printed with a numeric "dest" that would always be -1 (Broadcast) and that field is now removed from the printing.
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PacketPtr pkt = new Packet(req, cmd);
// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
pkt->senderState = new SenderState(m_address, req->getSize());
MEM: Separate requests and responses for timing accesses This patch moves send/recvTiming and send/recvTimingSnoop from the Port base class to the MasterPort and SlavePort, and also splits them into separate member functions for requests and responses: send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, send/recvTimingSnoopResp. A master port sends requests and receives responses, and also receives snoop requests and sends snoop responses. A slave port has the reciprocal behaviour as it receives requests and sends responses, and sends snoop requests and receives snoop responses. For all MemObjects that have only master ports or slave ports (but not both), e.g. a CPU, or a PIO device, this patch merely adds more clarity to what kind of access is taking place. For example, a CPU port used to call sendTiming, and will now call sendTimingReq. Similarly, a response previously came back through recvTiming, which is now recvTimingResp. For the modules that have both master and slave ports, e.g. the bus, the behaviour was previously relying on branches based on pkt->isRequest(), and this is now replaced with a direct call to the apprioriate member function depending on the type of access. Please note that send/recvRetry is still shared by all the timing accessors and remains in the Port base class for now (to maintain the current bus functionality and avoid changing the statistics of all regressions). The packet queue is split into a MasterPort and SlavePort version to facilitate the use of the new timing accessors. All uses of the PacketQueue are updated accordingly. With this patch, the type of packet (request or response) is now well defined for each type of access, and asserts on pkt->isRequest() and pkt->isResponse() are now moved to the appropriate send member functions. It is also worth noting that sendTimingSnoopReq no longer returns a boolean, as the semantics do not alow snoop requests to be rejected or stalled. All these assumptions are now excplicitly part of the port interface itself.
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if (port->sendTimingReq(pkt)) {
DPRINTF(RubyTest, "initiating Flush - successful\n");
}
}
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void
Check::initiateAction()
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{
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DPRINTF(RubyTest, "initiating Action\n");
assert(m_status == TesterStatus_Idle);
int index = random_mt.random(0, m_num_writers - 1);
MasterPort* port = m_tester_ptr->getWritableCpuPort(index);
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Request::Flags flags;
// Create the particular address for the next byte to be written
Addr writeAddr(m_address + m_store_count);
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// Stores are assumed to be 1 byte-sized
Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
curTick(), m_pc);
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req->setContext(index);
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Packet::Command cmd;
// 1 out of 8 chance, issue an atomic rather than a write
// if ((random() & 0x7) == 0) {
// cmd = MemCmd::SwapReq;
// } else {
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cmd = MemCmd::WriteReq;
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// }
MEM: Remove the Broadcast destination from the packet This patch simplifies the packet by removing the broadcast flag and instead more firmly relying on (and enforcing) the semantics of transactions in the classic memory system, i.e. request packets are routed from a master to a slave based on the address, and when they are created they have neither a valid source, nor destination. On their way to the slave, the request packet is updated with a source field for all modules that multiplex packets from multiple master (e.g. a bus). When a request packet is turned into a response packet (at the final slave), it moves the potentially populated source field to the destination field, and the response packet is routed through any multiplexing components back to the master based on the destination field. Modules that connect multiplexing components, such as caches and bridges store any existing source and destination field in the sender state as a stack (just as before). The packet constructor is simplified in that there is no longer a need to pass the Packet::Broadcast as the destination (this was always the case for the classic memory system). In the case of Ruby, rather than using the parameter to the constructor we now rely on setDest, as there is already another three-argument constructor in the packet class. In many places where the packet information was printed as part of DPRINTFs, request packets would be printed with a numeric "dest" that would always be -1 (Broadcast) and that field is now removed from the printing.
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PacketPtr pkt = new Packet(req, cmd);
uint8_t *writeData = new uint8_t[1];
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*writeData = m_value + m_store_count;
pkt->dataDynamic(writeData);
DPRINTF(RubyTest, "Seq write: index %d data 0x%x check 0x%x\n", index,
*(pkt->getConstPtr<uint8_t>()), *writeData);
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// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
pkt->senderState = new SenderState(writeAddr, req->getSize());
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MEM: Separate requests and responses for timing accesses This patch moves send/recvTiming and send/recvTimingSnoop from the Port base class to the MasterPort and SlavePort, and also splits them into separate member functions for requests and responses: send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, send/recvTimingSnoopResp. A master port sends requests and receives responses, and also receives snoop requests and sends snoop responses. A slave port has the reciprocal behaviour as it receives requests and sends responses, and sends snoop requests and receives snoop responses. For all MemObjects that have only master ports or slave ports (but not both), e.g. a CPU, or a PIO device, this patch merely adds more clarity to what kind of access is taking place. For example, a CPU port used to call sendTiming, and will now call sendTimingReq. Similarly, a response previously came back through recvTiming, which is now recvTimingResp. For the modules that have both master and slave ports, e.g. the bus, the behaviour was previously relying on branches based on pkt->isRequest(), and this is now replaced with a direct call to the apprioriate member function depending on the type of access. Please note that send/recvRetry is still shared by all the timing accessors and remains in the Port base class for now (to maintain the current bus functionality and avoid changing the statistics of all regressions). The packet queue is split into a MasterPort and SlavePort version to facilitate the use of the new timing accessors. All uses of the PacketQueue are updated accordingly. With this patch, the type of packet (request or response) is now well defined for each type of access, and asserts on pkt->isRequest() and pkt->isResponse() are now moved to the appropriate send member functions. It is also worth noting that sendTimingSnoopReq no longer returns a boolean, as the semantics do not alow snoop requests to be rejected or stalled. All these assumptions are now excplicitly part of the port interface itself.
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if (port->sendTimingReq(pkt)) {
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DPRINTF(RubyTest, "initiating action - successful\n");
DPRINTF(RubyTest, "status before action update: %s\n",
(TesterStatus_to_string(m_status)).c_str());
m_status = TesterStatus_Action_Pending;
DPRINTF(RubyTest, "Check %s, State=Action_Pending\n", m_address);
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} else {
// If the packet did not issue, must delete
// Note: No need to delete the data, the packet destructor
// will delete it
delete pkt->senderState;
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delete pkt->req;
delete pkt;
DPRINTF(RubyTest, "failed to initiate action - sequencer not ready\n");
}
DPRINTF(RubyTest, "status after action update: %s\n",
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(TesterStatus_to_string(m_status)).c_str());
}
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void
Check::initiateCheck()
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{
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DPRINTF(RubyTest, "Initiating Check\n");
assert(m_status == TesterStatus_Ready);
int index = random_mt.random(0, m_num_readers - 1);
MasterPort* port = m_tester_ptr->getReadableCpuPort(index);
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Request::Flags flags;
// If necessary, make the request an instruction fetch
if (m_tester_ptr->isInstOnlyCpuPort(index) ||
(m_tester_ptr->isInstDataCpuPort(index) &&
(random_mt.random(0, 0x1)))) {
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flags.set(Request::INST_FETCH);
}
// Checks are sized depending on the number of bytes written
Request *req = new Request(m_address, CHECK_SIZE, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
req->setContext(index);
MEM: Remove the Broadcast destination from the packet This patch simplifies the packet by removing the broadcast flag and instead more firmly relying on (and enforcing) the semantics of transactions in the classic memory system, i.e. request packets are routed from a master to a slave based on the address, and when they are created they have neither a valid source, nor destination. On their way to the slave, the request packet is updated with a source field for all modules that multiplex packets from multiple master (e.g. a bus). When a request packet is turned into a response packet (at the final slave), it moves the potentially populated source field to the destination field, and the response packet is routed through any multiplexing components back to the master based on the destination field. Modules that connect multiplexing components, such as caches and bridges store any existing source and destination field in the sender state as a stack (just as before). The packet constructor is simplified in that there is no longer a need to pass the Packet::Broadcast as the destination (this was always the case for the classic memory system). In the case of Ruby, rather than using the parameter to the constructor we now rely on setDest, as there is already another three-argument constructor in the packet class. In many places where the packet information was printed as part of DPRINTFs, request packets would be printed with a numeric "dest" that would always be -1 (Broadcast) and that field is now removed from the printing.
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PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
uint8_t *dataArray = new uint8_t[CHECK_SIZE];
pkt->dataDynamic(dataArray);
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DPRINTF(RubyTest, "Seq read: index %d\n", index);
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// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
pkt->senderState = new SenderState(m_address, req->getSize());
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MEM: Separate requests and responses for timing accesses This patch moves send/recvTiming and send/recvTimingSnoop from the Port base class to the MasterPort and SlavePort, and also splits them into separate member functions for requests and responses: send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, send/recvTimingSnoopResp. A master port sends requests and receives responses, and also receives snoop requests and sends snoop responses. A slave port has the reciprocal behaviour as it receives requests and sends responses, and sends snoop requests and receives snoop responses. For all MemObjects that have only master ports or slave ports (but not both), e.g. a CPU, or a PIO device, this patch merely adds more clarity to what kind of access is taking place. For example, a CPU port used to call sendTiming, and will now call sendTimingReq. Similarly, a response previously came back through recvTiming, which is now recvTimingResp. For the modules that have both master and slave ports, e.g. the bus, the behaviour was previously relying on branches based on pkt->isRequest(), and this is now replaced with a direct call to the apprioriate member function depending on the type of access. Please note that send/recvRetry is still shared by all the timing accessors and remains in the Port base class for now (to maintain the current bus functionality and avoid changing the statistics of all regressions). The packet queue is split into a MasterPort and SlavePort version to facilitate the use of the new timing accessors. All uses of the PacketQueue are updated accordingly. With this patch, the type of packet (request or response) is now well defined for each type of access, and asserts on pkt->isRequest() and pkt->isResponse() are now moved to the appropriate send member functions. It is also worth noting that sendTimingSnoopReq no longer returns a boolean, as the semantics do not alow snoop requests to be rejected or stalled. All these assumptions are now excplicitly part of the port interface itself.
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if (port->sendTimingReq(pkt)) {
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DPRINTF(RubyTest, "initiating check - successful\n");
DPRINTF(RubyTest, "status before check update: %s\n",
TesterStatus_to_string(m_status).c_str());
m_status = TesterStatus_Check_Pending;
DPRINTF(RubyTest, "Check %s, State=Check_Pending\n", m_address);
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} else {
// If the packet did not issue, must delete
// Note: No need to delete the data, the packet destructor
// will delete it
delete pkt->senderState;
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delete pkt->req;
delete pkt;
DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n");
}
DPRINTF(RubyTest, "status after check update: %s\n",
TesterStatus_to_string(m_status).c_str());
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}
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void
Check::performCallback(NodeID proc, SubBlock* data, Cycles curTime)
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{
Addr address = data->getAddress();
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// This isn't exactly right since we now have multi-byte checks
// assert(getAddress() == address);
assert(makeLineAddress(m_address) == makeLineAddress(address));
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assert(data != NULL);
DPRINTF(RubyTest, "RubyTester Callback\n");
debugPrint();
if (m_status == TesterStatus_Action_Pending) {
DPRINTF(RubyTest, "Action callback write value: %d, currently %d\n",
(m_value + m_store_count), data->getByte(0));
// Perform store one byte at a time
data->setByte(0, (m_value + m_store_count));
m_store_count++;
if (m_store_count == CHECK_SIZE) {
m_status = TesterStatus_Ready;
DPRINTF(RubyTest, "Check %s, State=Ready\n", m_address);
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} else {
m_status = TesterStatus_Idle;
DPRINTF(RubyTest, "Check %s, State=Idle store_count: %d\n",
m_address, m_store_count);
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}
DPRINTF(RubyTest, "Action callback return data now %d\n",
data->getByte(0));
} else if (m_status == TesterStatus_Check_Pending) {
DPRINTF(RubyTest, "Check callback\n");
// Perform load/check
for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) {
if (uint8_t(m_value + byte_number) != data->getByte(byte_number)) {
panic("Action/check failure: proc: %d address: %s data: %s "
"byte_number: %d m_value+byte_number: %d byte: %d %s"
"Time: %d\n",
proc, address, data, byte_number,
(int)m_value + byte_number,
(int)data->getByte(byte_number), *this, curTime);
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}
}
DPRINTF(RubyTest, "Action/check success\n");
debugPrint();
// successful check complete, increment complete
m_tester_ptr->incrementCheckCompletions();
m_status = TesterStatus_Idle;
DPRINTF(RubyTest, "Check %s, State=Idle\n", m_address);
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pickValue();
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} else {
panic("Unexpected TesterStatus: %s proc: %d data: %s m_status: %s "
"time: %d\n", *this, proc, data, m_status, curTime);
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}
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DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc,
makeLineAddress(m_address));
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DPRINTF(RubyTest, "Callback done\n");
debugPrint();
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}
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void
Check::changeAddress(Addr address)
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{
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assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
m_status = TesterStatus_Idle;
m_address = address;
DPRINTF(RubyTest, "Check %s, State=Idle\n", m_address);
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m_store_count = 0;
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}
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void
Check::pickValue()
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{
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assert(m_status == TesterStatus_Idle);
m_value = random_mt.random(0, 0xff); // One byte
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m_store_count = 0;
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}
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void
Check::pickInitiatingNode()
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{
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assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
m_status = TesterStatus_Idle;
m_initiatingNode = (random_mt.random(0, m_num_writers - 1));
DPRINTF(RubyTest, "Check %s, State=Idle, picked initiating node %d\n",
m_address, m_initiatingNode);
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m_store_count = 0;
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}
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void
Check::print(std::ostream& out) const
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{
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out << "["
<< m_address << ", value: "
<< (int)m_value << ", status: "
<< m_status << ", initiating node: "
<< m_initiatingNode << ", store_count: "
<< m_store_count
<< "]" << std::flush;
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}
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void
Check::debugPrint()
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{
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DPRINTF(RubyTest,
"[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n",
m_address, (int)m_value, TesterStatus_to_string(m_status).c_str(),
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m_initiatingNode, m_store_count);
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}