2010-08-20 20:46:13 +02:00
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2010-08-24 21:07:22 +02:00
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#include "cpu/testers/directedtest/InvalidateGenerator.hh"
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2016-11-09 21:27:37 +01:00
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2016-11-09 21:27:40 +01:00
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#include "base/trace.hh"
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2016-11-09 21:27:37 +01:00
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#include "cpu/testers/directedtest/DirectedGenerator.hh"
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2011-04-15 19:44:06 +02:00
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#include "cpu/testers/directedtest/RubyDirectedTester.hh"
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2011-04-15 19:44:32 +02:00
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#include "debug/DirectedTest.hh"
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2010-08-20 20:46:13 +02:00
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InvalidateGenerator::InvalidateGenerator(const Params *p)
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: DirectedGenerator(p)
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{
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//
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// First, issue loads to bring the block into S state
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//
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m_status = InvalidateGeneratorStatus_Load_Waiting;
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m_active_read_node = 0;
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m_active_inv_node = 0;
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m_address = 0x0;
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m_addr_increment_size = p->addr_increment_size;
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}
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InvalidateGenerator::~InvalidateGenerator()
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{
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}
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bool
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InvalidateGenerator::initiate()
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{
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2012-04-14 11:46:59 +02:00
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MasterPort* port;
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2010-08-20 20:46:13 +02:00
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Request::Flags flags;
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PacketPtr pkt;
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Packet::Command cmd;
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// For simplicity, requests are assumed to be 1 byte-sized
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2012-02-12 23:07:38 +01:00
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Request *req = new Request(m_address, 1, flags, masterId);
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2010-08-20 20:46:13 +02:00
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//
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// Based on the current state, issue a load or a store
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//
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if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
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DPRINTF(DirectedTest, "initiating read\n");
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cmd = MemCmd::ReadReq;
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2012-04-14 11:46:59 +02:00
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port = m_directed_tester->getCpuPort(m_active_read_node);
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MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
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pkt = new Packet(req, cmd);
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2010-08-20 20:46:13 +02:00
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} else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
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DPRINTF(DirectedTest, "initiating invalidating write\n");
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cmd = MemCmd::WriteReq;
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2012-04-14 11:46:59 +02:00
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port = m_directed_tester->getCpuPort(m_active_inv_node);
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MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
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pkt = new Packet(req, cmd);
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2010-08-20 20:46:13 +02:00
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} else {
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panic("initiate was unexpectedly called\n");
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}
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2014-12-02 12:07:43 +01:00
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pkt->allocate();
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2010-08-20 20:46:13 +02:00
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MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
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if (port->sendTimingReq(pkt)) {
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2010-08-20 20:46:13 +02:00
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DPRINTF(DirectedTest, "initiating request - successful\n");
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if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
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m_status = InvalidateGeneratorStatus_Load_Pending;
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} else {
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m_status = InvalidateGeneratorStatus_Inv_Pending;
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}
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return true;
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} else {
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// If the packet did not issue, must delete
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// Note: No need to delete the data, the packet destructor
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// will delete it
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delete pkt->req;
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delete pkt;
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DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n");
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return false;
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}
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}
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2016-02-07 02:21:18 +01:00
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void
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2012-01-10 01:08:20 +01:00
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InvalidateGenerator::performCallback(uint32_t proc, Addr address)
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2010-08-20 20:46:13 +02:00
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{
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2016-02-07 02:21:18 +01:00
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assert(m_address == address);
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2010-08-20 20:46:13 +02:00
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if (m_status == InvalidateGeneratorStatus_Load_Pending) {
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assert(m_active_read_node == proc);
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m_active_read_node++;
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//
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// Once all cpus have the block in S state, issue the invalidate
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//
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if (m_active_read_node == m_num_cpus) {
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m_status = InvalidateGeneratorStatus_Inv_Waiting;
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m_active_read_node = 0;
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} else {
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m_status = InvalidateGeneratorStatus_Load_Waiting;
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}
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} else if (m_status == InvalidateGeneratorStatus_Inv_Pending) {
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assert(m_active_inv_node == proc);
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m_active_inv_node++;
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if (m_active_inv_node == m_num_cpus) {
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m_address += m_addr_increment_size;
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m_active_inv_node = 0;
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}
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//
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// Invalidate completed, send that info to the tester and restart
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// the cycle
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//
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m_directed_tester->incrementCycleCompletions();
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m_status = InvalidateGeneratorStatus_Load_Waiting;
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2016-02-07 02:21:18 +01:00
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}
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2010-08-20 20:46:13 +02:00
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}
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InvalidateGenerator *
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InvalidateGeneratorParams::create()
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{
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return new InvalidateGenerator(this);
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}
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