gem5/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt

235 lines
26 KiB
Text
Raw Normal View History

---------- Begin Simulation Statistics ----------
host_inst_rate 472716 # Simulator instruction rate (inst/s)
host_mem_usage 197656 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 1037354119 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 10976 # Number of instructions simulated
sim_seconds 0.000024 # Number of seconds simulated
sim_ticks 24355000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1350000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1242000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1187 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2625000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.081269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2415000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 18.436620 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 2595 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 3975000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.057734 # miss rate for demand accesses
system.cpu.dcache.demand_misses 159 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.057734 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 159 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 2595 # number of overall hits
system.cpu.dcache.overall_miss_latency 3975000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.057734 # miss rate for overall accesses
system.cpu.dcache.overall_misses 159 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.057734 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 159 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 100.373888 # Cycle average of tags in use
system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24915.194346 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22915.194346 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 7051000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 6485000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 37.911661 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24915.194346 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency
system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 7051000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses
system.cpu.icache.demand_misses 283 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 6485000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24915.194346 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 10729 # number of overall hits
system.cpu.icache.overall_miss_latency 7051000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses
system.cpu.icache.overall_misses 283 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 6485000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 155.977710 # Cycle average of tags in use
system.cpu.icache.total_refs 10729 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1936000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 968000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 337 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 7370000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994065 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 335 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 3685000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994065 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 335 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 374000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 187000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.006289 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 425 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9306000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995294 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995294 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 425 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9306000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995294 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 423 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995294 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 178.108320 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 48710 # number of cpu cycles simulated
system.cpu.num_insts 10976 # Number of instructions executed
system.cpu.num_refs 2770 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------