2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2010-01-30 05:29:40 +01:00
|
|
|
sim_seconds 0.000123 # Number of seconds simulated
|
|
|
|
sim_ticks 123378 # Number of ticks simulated
|
2012-01-25 18:19:50 +01:00
|
|
|
final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
|
|
sim_freq 1000000000 # Frequency of simulated ticks
|
|
|
|
host_inst_rate 44691 # Simulator instruction rate (inst/s)
|
|
|
|
host_tick_rate 2138947 # Simulator tick rate (ticks/s)
|
|
|
|
host_mem_usage 216404 # Number of bytes of host memory used
|
|
|
|
host_seconds 0.06 # Real time elapsed on the host
|
|
|
|
sim_insts 2577 # Number of instructions simulated
|
|
|
|
system.physmem.bytes_read 13356 # Number of bytes read from this memory
|
|
|
|
system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
|
|
|
|
system.physmem.bytes_written 2058 # Number of bytes written to this memory
|
|
|
|
system.physmem.num_reads 3000 # Number of read requests responded to by this memory
|
|
|
|
system.physmem.num_writes 294 # Number of write requests responded to by this memory
|
|
|
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
|
|
|
system.physmem.bw_read 108252687 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_inst_read 83807486 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_write 16680445 # Write bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_total 124933132 # Total bandwidth to/from this memory (bytes/s)
|
2009-05-11 19:38:46 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2009-05-11 19:38:46 +02:00
|
|
|
system.cpu.dtb.read_hits 415 # DTB read hits
|
|
|
|
system.cpu.dtb.read_misses 4 # DTB read misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
|
|
system.cpu.dtb.read_accesses 419 # DTB read accesses
|
2009-05-11 19:38:46 +02:00
|
|
|
system.cpu.dtb.write_hits 294 # DTB write hits
|
|
|
|
system.cpu.dtb.write_misses 4 # DTB write misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
|
|
system.cpu.dtb.write_accesses 298 # DTB write accesses
|
|
|
|
system.cpu.dtb.data_hits 709 # DTB hits
|
|
|
|
system.cpu.dtb.data_misses 8 # DTB misses
|
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
|
|
system.cpu.dtb.data_accesses 717 # DTB accesses
|
2009-05-11 19:38:46 +02:00
|
|
|
system.cpu.itb.fetch_hits 2586 # ITB hits
|
|
|
|
system.cpu.itb.fetch_misses 11 # ITB misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
|
|
system.cpu.itb.fetch_accesses 2597 # ITB accesses
|
2009-05-11 19:38:46 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
2009-05-11 19:38:46 +02:00
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
system.cpu.workload.num_syscalls 4 # Number of system calls
|
2010-01-30 05:29:40 +01:00
|
|
|
system.cpu.numCycles 123378 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2009-05-11 19:38:46 +02:00
|
|
|
system.cpu.num_insts 2577 # Number of instructions executed
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
|
|
|
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
|
|
|
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_int_insts 2375 # number of integer instructions
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_fp_insts 6 # number of float instructions
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
|
|
|
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
|
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_mem_refs 717 # number of memory refs
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_load_insts 419 # Number of load instructions
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_store_insts 298 # Number of store instructions
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
|
|
system.cpu.num_busy_cycles 123378 # Number of busy cycles
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|