gem5/arch/sparc/isa/formats/branch.isa

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////////////////////////////////////////////////////////////////////
//
// Branch instructions
//
output header {{
/**
* Base class for branch operations.
*/
class Branch : public SparcStaticInst
{
protected:
// Constructor
Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for branch operations with an immediate displacement.
*/
class BranchDisp : public Branch
{
protected:
// Constructor
BranchDisp(const char *mnem, MachInst _machInst,
OpClass __opClass) :
Branch(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
int32_t disp;
};
/**
* Base class for branches with 19 bit displacements.
*/
class Branch19 : public BranchDisp
{
protected:
// Constructor
Branch19(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext(DISP19 << 2, 21);
}
};
/**
* Base class for branches with 22 bit displacements.
*/
class Branch22 : public BranchDisp
{
protected:
// Constructor
Branch22(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext(DISP22 << 2, 24);
}
};
/**
* Base class for branches with 30 bit displacements.
*/
class Branch30 : public BranchDisp
{
protected:
// Constructor
Branch30(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext(DISP30 << 2, 32);
}
};
/**
* Base class for 16bit split displacements.
*/
class BranchSplit : public BranchDisp
{
protected:
// Constructor
BranchSplit(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
}
};
/**
* Base class for branches that use an immediate and a register to
* compute their displacements.
*/
class BranchImm13 : public Branch
{
protected:
// Constructor
BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
int32_t imm;
};
}};
output decoder {{
std::string Branch::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
if (_numSrcRegs > 0)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if (_numDestRegs > 0)
{
if(_numSrcRegs > 0)
response << ", ";
printReg(response, _destRegIdx[0]);
}
return response.str();
}
std::string BranchImm13::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
if (_numSrcRegs > 0)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if(_numSrcRegs > 0)
response << ", ";
ccprintf(response, "0x%x", imm);
if (_numDestRegs > 0)
{
response << ", ";
printReg(response, _destRegIdx[0]);
}
return response.str();
}
std::string BranchDisp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
std::string symbol;
Addr symbolAddr;
Addr target = disp + pc;
printMnemonic(response, mnemonic);
ccprintf(response, "0x%x", target);
if(symtab->findNearestSymbol(target, symbol, symbolAddr))
{
ccprintf(response, " <%s", symbol);
if(symbolAddr != target)
ccprintf(response, "+%d>", target - symbolAddr);
else
ccprintf(response, ">");
}
return response.str();
}
}};
def template BranchExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
//Attempt to execute the instruction
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
NNPC = xc->readNextNPC();
%(code)s;
if(fault == NoFault)
{
//Write the resulting state to the execution context
%(op_wb)s;
}
return fault;
}
}};
let {{
handle_annul = '''
{
if(A)
{
NPC = xc->readNextNPC();
NNPC = NPC + 4;
}
else
{
NPC = xc->readNextPC();
NNPC = xc->readNextNPC();
}
}'''
}};
// Primary format for branch instructions:
def format Branch(code, *opt_flags) {{
code = re.sub(r'handle_annul', handle_annul, code)
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
Fixes to SPARC syscall emulation mode. arch/sparc/isa/base.isa: Added a set of abbreviations for the different condition tests. arch/sparc/isa/decoder.isa: Fixes and additions to get syscall emulation closer to working. arch/sparc/isa/formats/branch.isa: Fixed branches so that the immediate version actually uses the immediate value arch/sparc/isa/formats/integerop.isa: Compute the condition codes -before- writing to the state of the machine. arch/sparc/isa/formats/mem.isa: An attempt to fix up the output of the disassembly of loads and stores. arch/sparc/isa/formats/trap.isa: Added code to disassemble a trap instruction. This probably needs to be fixed up so there are immediate and register versions. arch/sparc/isa/operands.isa: Added an R1 operand, and fixed up the numbering arch/sparc/isa_traits.hh: SyscallNumReg is no longer needed, the max number of sources and destinations are fixed up, and the syscall return uses xcc instead of icc. arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: Added a getresuidFunc syscall implementation. This isn't actually used, but I thought it was and will leave it in. arch/sparc/process.cc: arch/sparc/process.hh: Fixed up how the initial stack frame is set up. arch/sparc/regfile.hh: Changed the number of windows from 6 to 32 so we don't have to worry about spill and fill traps for now, and commented out the register file setting itself up. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Changed the syscall mechanism to pass down the syscall number directly. --HG-- extra : convert_revision : 15723b949a0ddb3d24e68c079343b4dba2439f43
2006-04-18 15:27:22 +02:00
iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
if usesImm:
imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
Fixes to SPARC syscall emulation mode. arch/sparc/isa/base.isa: Added a set of abbreviations for the different condition tests. arch/sparc/isa/decoder.isa: Fixes and additions to get syscall emulation closer to working. arch/sparc/isa/formats/branch.isa: Fixed branches so that the immediate version actually uses the immediate value arch/sparc/isa/formats/integerop.isa: Compute the condition codes -before- writing to the state of the machine. arch/sparc/isa/formats/mem.isa: An attempt to fix up the output of the disassembly of loads and stores. arch/sparc/isa/formats/trap.isa: Added code to disassemble a trap instruction. This probably needs to be fixed up so there are immediate and register versions. arch/sparc/isa/operands.isa: Added an R1 operand, and fixed up the numbering arch/sparc/isa_traits.hh: SyscallNumReg is no longer needed, the max number of sources and destinations are fixed up, and the syscall return uses xcc instead of icc. arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: Added a getresuidFunc syscall implementation. This isn't actually used, but I thought it was and will leave it in. arch/sparc/process.cc: arch/sparc/process.hh: Fixed up how the initial stack frame is set up. arch/sparc/regfile.hh: Changed the number of windows from 6 to 32 so we don't have to worry about spill and fill traps for now, and commented out the register file setting itself up. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Changed the syscall mechanism to pass down the syscall number directly. --HG-- extra : convert_revision : 15723b949a0ddb3d24e68c079343b4dba2439f43
2006-04-18 15:27:22 +02:00
immCode, opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += BranchExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format Branch19(code, *opt_flags) {{
code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format Branch22(code, *opt_flags) {{
code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format Branch30(code, *opt_flags) {{
code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format BranchSplit(code, *opt_flags) {{
code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};