2006-06-28 17:02:14 +02:00
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/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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*/
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/**
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* @file
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* Miss and writeback queue declarations.
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*/
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#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
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#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
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#include <list>
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2006-12-19 06:53:06 +01:00
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#include "base/statistics.hh"
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#include "mem/packet.hh"
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2006-06-28 17:02:14 +02:00
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class BaseCache;
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2006-12-19 06:53:06 +01:00
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2006-06-28 17:02:14 +02:00
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class BasePrefetcher
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{
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protected:
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/** The Prefetch Queue. */
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2006-10-20 09:10:12 +02:00
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std::list<PacketPtr> pf;
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2006-06-28 17:02:14 +02:00
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// PARAMETERS
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/** The number of MSHRs in the Prefetch Queue. */
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const int size;
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/** Pointr to the parent cache. */
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BaseCache* cache;
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/** The block size of the parent cache. */
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int blkSize;
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/** Do we prefetch across page boundaries. */
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bool pageStop;
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/** Do we remove prefetches with later times than a new miss.*/
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bool serialSquash;
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/** Do we check if it is in the cache when inserting into buffer,
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or removing.*/
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bool cacheCheckPush;
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/** Do we prefetch on only data reads, or on inst reads as well. */
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bool only_data;
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public:
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Stats::Scalar<> pfIdentified;
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Stats::Scalar<> pfMSHRHit;
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Stats::Scalar<> pfCacheHit;
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Stats::Scalar<> pfBufferHit;
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Stats::Scalar<> pfRemovedFull;
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Stats::Scalar<> pfRemovedMSHR;
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Stats::Scalar<> pfIssued;
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Stats::Scalar<> pfSpanPage;
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Stats::Scalar<> pfSquashed;
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void regStats(const std::string &name);
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public:
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BasePrefetcher(int numMSHRS, bool pageStop, bool serialSquash,
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bool cacheCheckPush, bool onlyData);
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virtual ~BasePrefetcher() {}
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void setCache(BaseCache *_cache);
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2006-10-20 09:10:12 +02:00
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void handleMiss(PacketPtr &pkt, Tick time);
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2006-06-28 17:02:14 +02:00
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2006-12-19 06:53:06 +01:00
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bool inCache(Addr addr);
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bool inMissQueue(Addr addr);
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2006-10-20 09:10:12 +02:00
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PacketPtr getPacket();
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2006-06-28 17:02:14 +02:00
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bool havePending()
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{
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return !pf.empty();
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}
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2006-10-20 09:10:12 +02:00
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virtual void calculatePrefetch(PacketPtr &pkt,
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2006-06-28 17:02:14 +02:00
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std::list<Addr> &addresses,
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std::list<Tick> &delays) = 0;
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2006-10-20 09:10:12 +02:00
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std::list<PacketPtr>::iterator inPrefetch(Addr address);
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2006-06-28 17:02:14 +02:00
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};
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#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
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