2010-06-02 19:58:16 +02:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2010 ARM Limited
|
|
|
|
* All rights reserved
|
|
|
|
*
|
|
|
|
* The license below extends only to copyright in the software and shall
|
|
|
|
* not be construed as granting a license to any other intellectual
|
|
|
|
* property including but not limited to intellectual property relating
|
|
|
|
* to a hardware implementation of the functionality of the software
|
|
|
|
* licensed hereunder. You may use the software subject to the license
|
|
|
|
* terms below provided that you ensure that this notice is replicated
|
|
|
|
* unmodified and in its entirety in all distributions of the software,
|
|
|
|
* modified or unmodified, in source code or in binary form.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are
|
|
|
|
* met: redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer;
|
|
|
|
* redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution;
|
|
|
|
* neither the name of the copyright holders nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived from
|
|
|
|
* this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*
|
|
|
|
* Authors: Ali Saidi
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "arch/arm/faults.hh"
|
|
|
|
#include "arch/arm/table_walker.hh"
|
|
|
|
#include "arch/arm/tlb.hh"
|
2010-11-08 20:58:24 +01:00
|
|
|
#include "cpu/base.hh"
|
2010-06-02 19:58:16 +02:00
|
|
|
#include "cpu/thread_context.hh"
|
2011-04-21 03:45:03 +02:00
|
|
|
#include "debug/Checkpoint.hh"
|
2012-08-15 16:38:08 +02:00
|
|
|
#include "debug/Drain.hh"
|
2011-04-21 03:45:03 +02:00
|
|
|
#include "debug/TLB.hh"
|
|
|
|
#include "debug/TLBVerbose.hh"
|
2010-11-15 21:04:03 +01:00
|
|
|
#include "sim/system.hh"
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
using namespace ArmISA;
|
|
|
|
|
|
|
|
TableWalker::TableWalker(const Params *p)
|
2012-08-22 17:39:59 +02:00
|
|
|
: MemObject(p), port(this, params()->sys), drainEvent(NULL),
|
2012-02-24 17:43:53 +01:00
|
|
|
tlb(NULL), currState(NULL), pending(false),
|
2012-02-12 23:07:38 +01:00
|
|
|
masterId(p->sys->getMasterId(name())),
|
2012-09-25 18:49:40 +02:00
|
|
|
numSquashable(p->num_squash_per_cycle),
|
2010-11-08 20:58:24 +01:00
|
|
|
doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
|
2010-06-02 19:58:18 +02:00
|
|
|
{
|
2010-08-23 18:18:39 +02:00
|
|
|
sctlr = 0;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
TableWalker::~TableWalker()
|
|
|
|
{
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
2012-08-15 16:38:08 +02:00
|
|
|
void
|
|
|
|
TableWalker::completeDrain()
|
|
|
|
{
|
|
|
|
if (drainEvent && stateQueueL1.empty() && stateQueueL2.empty() &&
|
|
|
|
pendingQueue.empty()) {
|
|
|
|
changeState(Drained);
|
|
|
|
DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
|
|
|
|
drainEvent->process();
|
|
|
|
drainEvent = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-15 21:04:03 +01:00
|
|
|
unsigned int
|
|
|
|
TableWalker::drain(Event *de)
|
2010-06-02 19:58:16 +02:00
|
|
|
{
|
2012-08-15 16:38:08 +02:00
|
|
|
unsigned int count = port.drain(de);
|
|
|
|
|
|
|
|
if (stateQueueL1.empty() && stateQueueL2.empty() &&
|
|
|
|
pendingQueue.empty()) {
|
2010-11-08 20:58:25 +01:00
|
|
|
changeState(Drained);
|
2012-08-15 16:38:08 +02:00
|
|
|
DPRINTF(Drain, "TableWalker free, no need to drain\n");
|
|
|
|
|
|
|
|
// table walker is drained, but its ports may still need to be drained
|
|
|
|
return count;
|
|
|
|
} else {
|
|
|
|
drainEvent = de;
|
|
|
|
changeState(Draining);
|
|
|
|
DPRINTF(Drain, "TableWalker not drained\n");
|
|
|
|
|
|
|
|
// return port drain count plus the table walker itself needs to drain
|
|
|
|
return count + 1;
|
|
|
|
|
2010-11-08 20:58:25 +01:00
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
2010-11-15 21:04:03 +01:00
|
|
|
void
|
|
|
|
TableWalker::resume()
|
|
|
|
{
|
|
|
|
MemObject::resume();
|
|
|
|
if ((params()->sys->getMemoryMode() == Enums::timing) && currState) {
|
2012-08-15 16:38:08 +02:00
|
|
|
delete currState;
|
|
|
|
currState = NULL;
|
2010-11-15 21:04:03 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
MasterPort&
|
|
|
|
TableWalker::getMasterPort(const std::string &if_name, int idx)
|
2010-06-02 19:58:16 +02:00
|
|
|
{
|
|
|
|
if (if_name == "port") {
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return port;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return MemObject::getMasterPort(if_name, idx);
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
Fault
|
2010-06-02 19:58:18 +02:00
|
|
|
TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode,
|
2012-01-31 16:46:03 +01:00
|
|
|
TLB::Translation *_trans, bool _timing, bool _functional)
|
2010-06-02 19:58:16 +02:00
|
|
|
{
|
2012-01-31 16:46:03 +01:00
|
|
|
assert(!(_functional && _timing));
|
2010-06-02 19:58:18 +02:00
|
|
|
if (!currState) {
|
|
|
|
// For atomic mode, a new WalkerState instance should be only created
|
|
|
|
// once per TLB. For timing mode, a new instance is generated for every
|
|
|
|
// TLB miss.
|
|
|
|
DPRINTF(TLBVerbose, "creating new instance of WalkerState\n");
|
|
|
|
|
|
|
|
currState = new WalkerState();
|
|
|
|
currState->tableWalker = this;
|
2011-04-04 18:42:27 +02:00
|
|
|
} else if (_timing) {
|
|
|
|
// This is a translation that was completed and then faulted again
|
|
|
|
// because some underlying parameters that affect the translation
|
|
|
|
// changed out from under us (e.g. asid). It will either be a
|
|
|
|
// misprediction, in which case nothing will happen or we'll use
|
|
|
|
// this fault to re-execute the faulting instruction which should clean
|
|
|
|
// up everything.
|
|
|
|
if (currState->vaddr == _req->getVaddr()) {
|
|
|
|
return new ReExec;
|
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
panic("currState should always be empty in timing mode!\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
currState->tc = _tc;
|
|
|
|
currState->transState = _trans;
|
|
|
|
currState->req = _req;
|
|
|
|
currState->fault = NoFault;
|
|
|
|
currState->contextId = _cid;
|
|
|
|
currState->timing = _timing;
|
2012-01-31 16:46:03 +01:00
|
|
|
currState->functional = _functional;
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->mode = _mode;
|
2010-06-02 19:58:16 +02:00
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
/** @todo These should be cached or grabbed from cached copies in
|
|
|
|
the TLB, all these miscreg reads are expensive */
|
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.
Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
|
|
|
currState->vaddr = currState->req->getVaddr();
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR);
|
|
|
|
sctlr = currState->sctlr;
|
|
|
|
currState->N = currState->tc->readMiscReg(MISCREG_TTBCR);
|
2010-06-02 19:58:16 +02:00
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->isFetch = (currState->mode == TLB::Execute);
|
|
|
|
currState->isWrite = (currState->mode == TLB::Write);
|
|
|
|
|
2010-11-08 20:58:24 +01:00
|
|
|
|
|
|
|
if (!currState->timing)
|
|
|
|
return processWalk();
|
|
|
|
|
2011-02-23 22:10:49 +01:00
|
|
|
if (pending || pendingQueue.size()) {
|
2010-11-08 20:58:24 +01:00
|
|
|
pendingQueue.push_back(currState);
|
|
|
|
currState = NULL;
|
|
|
|
} else {
|
|
|
|
pending = true;
|
2011-02-23 22:10:49 +01:00
|
|
|
return processWalk();
|
2010-11-08 20:58:24 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TableWalker::processWalkWrapper()
|
|
|
|
{
|
|
|
|
assert(!currState);
|
|
|
|
assert(pendingQueue.size());
|
|
|
|
currState = pendingQueue.front();
|
2012-09-25 18:49:40 +02:00
|
|
|
|
|
|
|
|
|
|
|
if (!currState->transState->squashed()) {
|
|
|
|
// We've got a valid request, lets process it
|
|
|
|
pending = true;
|
|
|
|
pendingQueue.pop_front();
|
|
|
|
processWalk();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// If the instruction that we were translating for has been
|
|
|
|
// squashed we shouldn't bother.
|
|
|
|
unsigned num_squashed = 0;
|
|
|
|
ThreadContext *tc = currState->tc;
|
|
|
|
assert(currState->transState->squashed());
|
|
|
|
while ((num_squashed < numSquashable) && currState &&
|
|
|
|
currState->transState->squashed()) {
|
|
|
|
pendingQueue.pop_front();
|
|
|
|
num_squashed++;
|
|
|
|
|
|
|
|
DPRINTF(TLB, "Squashing table walk for address %#x\n", currState->vaddr);
|
|
|
|
|
|
|
|
// finish the translation which will delete the translation object
|
|
|
|
currState->transState->finish(new UnimpFault("Squashed Inst"),
|
|
|
|
currState->req, currState->tc, currState->mode);
|
|
|
|
|
|
|
|
// delete the current request
|
|
|
|
delete currState;
|
|
|
|
|
|
|
|
// peak at the next one
|
|
|
|
if (pendingQueue.size())
|
|
|
|
currState = pendingQueue.front();
|
|
|
|
else
|
|
|
|
currState = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
// if we've still got pending translations schedule more work
|
|
|
|
nextWalk(tc);
|
|
|
|
currState = NULL;
|
2010-11-08 20:58:24 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Fault
|
|
|
|
TableWalker::processWalk()
|
|
|
|
{
|
2010-06-02 19:58:18 +02:00
|
|
|
Addr ttbr = 0;
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
// If translation isn't enabled, we shouldn't be here
|
2010-06-02 19:58:18 +02:00
|
|
|
assert(currState->sctlr.m);
|
2010-06-02 19:58:16 +02:00
|
|
|
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n",
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->vaddr, currState->N, mbits(currState->vaddr, 31,
|
|
|
|
32-currState->N));
|
2010-06-02 19:58:16 +02:00
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) {
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, " - Selecting TTBR0\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
ttbr = currState->tc->readMiscReg(MISCREG_TTBR0);
|
2010-06-02 19:58:16 +02:00
|
|
|
} else {
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, " - Selecting TTBR1\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
ttbr = currState->tc->readMiscReg(MISCREG_TTBR1);
|
|
|
|
currState->N = 0;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) |
|
|
|
|
(bits(currState->vaddr,31-currState->N,20) << 2);
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr);
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
|
|
|
|
// Trickbox address check
|
2010-06-02 19:58:18 +02:00
|
|
|
Fault f;
|
|
|
|
f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t),
|
|
|
|
currState->isFetch, currState->isWrite, 0, true);
|
|
|
|
if (f) {
|
2011-02-23 22:10:49 +01:00
|
|
|
DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr);
|
2010-08-23 18:18:39 +02:00
|
|
|
if (currState->timing) {
|
2010-11-08 20:58:24 +01:00
|
|
|
pending = false;
|
|
|
|
nextWalk(currState->tc);
|
2010-08-23 18:18:39 +02:00
|
|
|
currState = NULL;
|
|
|
|
} else {
|
|
|
|
currState->tc = NULL;
|
|
|
|
currState->req = NULL;
|
|
|
|
}
|
|
|
|
return f;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
2011-02-12 01:29:35 +01:00
|
|
|
Request::Flags flag = 0;
|
|
|
|
if (currState->sctlr.c == 0) {
|
|
|
|
flag = Request::UNCACHEABLE;
|
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->timing) {
|
2012-02-24 17:43:53 +01:00
|
|
|
port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
|
|
|
|
&doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
|
2012-08-28 20:30:33 +02:00
|
|
|
currState->tc->getCpuPtr()->clockPeriod(), flag);
|
|
|
|
DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before "
|
|
|
|
"adding: %d\n",
|
2010-08-26 02:10:43 +02:00
|
|
|
stateQueueL1.size());
|
|
|
|
stateQueueL1.push_back(currState);
|
2010-06-02 19:58:18 +02:00
|
|
|
currState = NULL;
|
2012-01-31 16:46:03 +01:00
|
|
|
} else if (!currState->functional) {
|
2012-02-24 17:43:53 +01:00
|
|
|
port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
|
|
|
|
NULL, (uint8_t*)&currState->l1Desc.data,
|
2012-08-28 20:30:33 +02:00
|
|
|
currState->tc->getCpuPtr()->clockPeriod(), flag);
|
2010-06-02 19:58:16 +02:00
|
|
|
doL1Descriptor();
|
2010-06-02 19:58:18 +02:00
|
|
|
f = currState->fault;
|
2012-01-31 16:46:03 +01:00
|
|
|
} else {
|
2012-02-12 23:07:38 +01:00
|
|
|
RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
|
MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
|
|
|
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
|
2012-01-31 16:46:03 +01:00
|
|
|
pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
|
2012-02-24 17:43:53 +01:00
|
|
|
port.sendFunctional(pkt);
|
2012-01-31 16:46:03 +01:00
|
|
|
doL1Descriptor();
|
|
|
|
delete req;
|
|
|
|
delete pkt;
|
|
|
|
f = currState->fault;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
return f;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2010-06-02 19:58:18 +02:00
|
|
|
TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
|
|
|
|
uint8_t texcb, bool s)
|
2010-06-02 19:58:16 +02:00
|
|
|
{
|
2010-06-02 19:58:18 +02:00
|
|
|
// Note: tc and sctlr local variables are hiding tc and sctrl class
|
|
|
|
// variables
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s);
|
|
|
|
te.shareable = false; // default value
|
2010-08-23 18:18:39 +02:00
|
|
|
te.nonCacheable = false;
|
2010-06-02 19:58:18 +02:00
|
|
|
bool outer_shareable = false;
|
2010-06-02 19:58:18 +02:00
|
|
|
if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) {
|
2010-06-02 19:58:16 +02:00
|
|
|
switch(texcb) {
|
2010-06-02 19:58:18 +02:00
|
|
|
case 0: // Stongly-ordered
|
|
|
|
te.nonCacheable = true;
|
|
|
|
te.mtype = TlbEntry::StronglyOrdered;
|
|
|
|
te.shareable = true;
|
|
|
|
te.innerAttrs = 1;
|
|
|
|
te.outerAttrs = 0;
|
|
|
|
break;
|
|
|
|
case 1: // Shareable Device
|
2010-06-02 19:58:16 +02:00
|
|
|
te.nonCacheable = true;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.mtype = TlbEntry::Device;
|
|
|
|
te.shareable = true;
|
|
|
|
te.innerAttrs = 3;
|
|
|
|
te.outerAttrs = 0;
|
|
|
|
break;
|
|
|
|
case 2: // Outer and Inner Write-Through, no Write-Allocate
|
|
|
|
te.mtype = TlbEntry::Normal;
|
|
|
|
te.shareable = s;
|
|
|
|
te.innerAttrs = 6;
|
|
|
|
te.outerAttrs = bits(texcb, 1, 0);
|
|
|
|
break;
|
|
|
|
case 3: // Outer and Inner Write-Back, no Write-Allocate
|
|
|
|
te.mtype = TlbEntry::Normal;
|
|
|
|
te.shareable = s;
|
|
|
|
te.innerAttrs = 7;
|
|
|
|
te.outerAttrs = bits(texcb, 1, 0);
|
|
|
|
break;
|
|
|
|
case 4: // Outer and Inner Non-cacheable
|
|
|
|
te.nonCacheable = true;
|
|
|
|
te.mtype = TlbEntry::Normal;
|
|
|
|
te.shareable = s;
|
|
|
|
te.innerAttrs = 0;
|
|
|
|
te.outerAttrs = bits(texcb, 1, 0);
|
|
|
|
break;
|
|
|
|
case 5: // Reserved
|
2010-06-02 19:58:18 +02:00
|
|
|
panic("Reserved texcb value!\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
break;
|
|
|
|
case 6: // Implementation Defined
|
2010-06-02 19:58:18 +02:00
|
|
|
panic("Implementation-defined texcb value!\n");
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
2010-06-02 19:58:18 +02:00
|
|
|
case 7: // Outer and Inner Write-Back, Write-Allocate
|
|
|
|
te.mtype = TlbEntry::Normal;
|
|
|
|
te.shareable = s;
|
|
|
|
te.innerAttrs = 5;
|
|
|
|
te.outerAttrs = 1;
|
|
|
|
break;
|
|
|
|
case 8: // Non-shareable Device
|
|
|
|
te.nonCacheable = true;
|
|
|
|
te.mtype = TlbEntry::Device;
|
|
|
|
te.shareable = false;
|
|
|
|
te.innerAttrs = 3;
|
|
|
|
te.outerAttrs = 0;
|
|
|
|
break;
|
|
|
|
case 9 ... 15: // Reserved
|
2010-06-02 19:58:18 +02:00
|
|
|
panic("Reserved texcb value!\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
break;
|
|
|
|
case 16 ... 31: // Cacheable Memory
|
|
|
|
te.mtype = TlbEntry::Normal;
|
|
|
|
te.shareable = s;
|
2010-06-02 19:58:16 +02:00
|
|
|
if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0)
|
|
|
|
te.nonCacheable = true;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.innerAttrs = bits(texcb, 1, 0);
|
|
|
|
te.outerAttrs = bits(texcb, 3, 2);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
2010-06-02 19:58:18 +02:00
|
|
|
default:
|
|
|
|
panic("More than 32 states for 5 bits?\n");
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
} else {
|
2010-06-02 19:58:18 +02:00
|
|
|
assert(tc);
|
2010-06-02 19:58:16 +02:00
|
|
|
PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
|
|
|
|
NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
|
2010-08-23 18:18:39 +02:00
|
|
|
uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0;
|
2010-06-02 19:58:16 +02:00
|
|
|
switch(bits(texcb, 2,0)) {
|
|
|
|
case 0:
|
2010-06-02 19:58:18 +02:00
|
|
|
curr_tr = prrr.tr0;
|
|
|
|
curr_ir = nmrr.ir0;
|
|
|
|
curr_or = nmrr.or0;
|
|
|
|
outer_shareable = (prrr.nos0 == 0);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
|
|
|
case 1:
|
2010-06-02 19:58:18 +02:00
|
|
|
curr_tr = prrr.tr1;
|
|
|
|
curr_ir = nmrr.ir1;
|
|
|
|
curr_or = nmrr.or1;
|
|
|
|
outer_shareable = (prrr.nos1 == 0);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
|
|
|
case 2:
|
2010-06-02 19:58:18 +02:00
|
|
|
curr_tr = prrr.tr2;
|
|
|
|
curr_ir = nmrr.ir2;
|
|
|
|
curr_or = nmrr.or2;
|
|
|
|
outer_shareable = (prrr.nos2 == 0);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
|
|
|
case 3:
|
2010-06-02 19:58:18 +02:00
|
|
|
curr_tr = prrr.tr3;
|
|
|
|
curr_ir = nmrr.ir3;
|
|
|
|
curr_or = nmrr.or3;
|
|
|
|
outer_shareable = (prrr.nos3 == 0);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
|
|
|
case 4:
|
2010-06-02 19:58:18 +02:00
|
|
|
curr_tr = prrr.tr4;
|
|
|
|
curr_ir = nmrr.ir4;
|
|
|
|
curr_or = nmrr.or4;
|
|
|
|
outer_shareable = (prrr.nos4 == 0);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
|
|
|
case 5:
|
2010-06-02 19:58:18 +02:00
|
|
|
curr_tr = prrr.tr5;
|
|
|
|
curr_ir = nmrr.ir5;
|
|
|
|
curr_or = nmrr.or5;
|
|
|
|
outer_shareable = (prrr.nos5 == 0);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
panic("Imp defined type\n");
|
|
|
|
case 7:
|
2010-06-02 19:58:18 +02:00
|
|
|
curr_tr = prrr.tr7;
|
|
|
|
curr_ir = nmrr.ir7;
|
|
|
|
curr_or = nmrr.or7;
|
|
|
|
outer_shareable = (prrr.nos7 == 0);
|
2010-06-02 19:58:16 +02:00
|
|
|
break;
|
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
|
|
|
|
switch(curr_tr) {
|
|
|
|
case 0:
|
|
|
|
DPRINTF(TLBVerbose, "StronglyOrdered\n");
|
|
|
|
te.mtype = TlbEntry::StronglyOrdered;
|
|
|
|
te.nonCacheable = true;
|
|
|
|
te.innerAttrs = 1;
|
|
|
|
te.outerAttrs = 0;
|
|
|
|
te.shareable = true;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n",
|
|
|
|
prrr.ds1, prrr.ds0, s);
|
|
|
|
te.mtype = TlbEntry::Device;
|
|
|
|
te.nonCacheable = true;
|
|
|
|
te.innerAttrs = 3;
|
|
|
|
te.outerAttrs = 0;
|
|
|
|
if (prrr.ds1 && s)
|
|
|
|
te.shareable = true;
|
|
|
|
if (prrr.ds0 && !s)
|
|
|
|
te.shareable = true;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n",
|
|
|
|
prrr.ns1, prrr.ns0, s);
|
|
|
|
te.mtype = TlbEntry::Normal;
|
|
|
|
if (prrr.ns1 && s)
|
|
|
|
te.shareable = true;
|
|
|
|
if (prrr.ns0 && !s)
|
|
|
|
te.shareable = true;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
panic("Reserved type");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (te.mtype == TlbEntry::Normal){
|
|
|
|
switch(curr_ir) {
|
|
|
|
case 0:
|
|
|
|
te.nonCacheable = true;
|
|
|
|
te.innerAttrs = 0;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
te.innerAttrs = 5;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
te.innerAttrs = 6;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
te.innerAttrs = 7;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch(curr_or) {
|
|
|
|
case 0:
|
|
|
|
te.nonCacheable = true;
|
|
|
|
te.outerAttrs = 0;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
te.outerAttrs = 1;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
te.outerAttrs = 2;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
te.outerAttrs = 3;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \
|
|
|
|
outerAttrs: %d\n",
|
|
|
|
te.shareable, te.innerAttrs, te.outerAttrs);
|
2010-06-02 19:58:18 +02:00
|
|
|
|
|
|
|
/** Formatting for Physical Address Register (PAR)
|
|
|
|
* Only including lower bits (TLB info here)
|
|
|
|
* PAR:
|
|
|
|
* PA [31:12]
|
|
|
|
* Reserved [11]
|
|
|
|
* TLB info [10:1]
|
|
|
|
* NOS [10] (Not Outer Sharable)
|
|
|
|
* NS [9] (Non-Secure)
|
|
|
|
* -- [8] (Implementation Defined)
|
|
|
|
* SH [7] (Sharable)
|
|
|
|
* Inner[6:4](Inner memory attributes)
|
|
|
|
* Outer[3:2](Outer memory attributes)
|
|
|
|
* SS [1] (SuperSection)
|
|
|
|
* F [0] (Fault, Fault Status in [6:1] if faulted)
|
|
|
|
*/
|
|
|
|
te.attributes = (
|
|
|
|
((outer_shareable ? 0:1) << 10) |
|
|
|
|
// TODO: NS Bit
|
|
|
|
((te.shareable ? 1:0) << 7) |
|
|
|
|
(te.innerAttrs << 4) |
|
|
|
|
(te.outerAttrs << 2)
|
|
|
|
// TODO: Supersection bit
|
|
|
|
// TODO: Fault bit
|
|
|
|
);
|
|
|
|
|
|
|
|
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TableWalker::doL1Descriptor()
|
|
|
|
{
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
|
|
|
|
currState->vaddr, currState->l1Desc.data);
|
2010-06-02 19:58:16 +02:00
|
|
|
TlbEntry te;
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
switch (currState->l1Desc.type()) {
|
2010-06-02 19:58:16 +02:00
|
|
|
case L1Descriptor::Ignore:
|
|
|
|
case L1Descriptor::Reserved:
|
2011-02-12 01:29:35 +01:00
|
|
|
if (!currState->timing) {
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->tc = NULL;
|
|
|
|
currState->req = NULL;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->isFetch)
|
|
|
|
currState->fault =
|
|
|
|
new PrefetchAbort(currState->vaddr, ArmFault::Translation0);
|
2010-06-02 19:58:16 +02:00
|
|
|
else
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->fault =
|
2010-08-23 18:18:39 +02:00
|
|
|
new DataAbort(currState->vaddr, 0, currState->isWrite,
|
2010-06-02 19:58:18 +02:00
|
|
|
ArmFault::Translation0);
|
2010-06-02 19:58:16 +02:00
|
|
|
return;
|
|
|
|
case L1Descriptor::Section:
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) {
|
2010-06-02 19:58:18 +02:00
|
|
|
/** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is
|
|
|
|
* enabled if set, do l1.Desc.setAp0() instead of generating
|
|
|
|
* AccessFlag0
|
|
|
|
*/
|
|
|
|
|
2010-08-23 18:18:41 +02:00
|
|
|
currState->fault = new DataAbort(currState->vaddr,
|
|
|
|
currState->l1Desc.domain(), currState->isWrite,
|
2010-06-02 19:58:18 +02:00
|
|
|
ArmFault::AccessFlag0);
|
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->l1Desc.supersection()) {
|
2010-06-02 19:58:16 +02:00
|
|
|
panic("Haven't implemented supersections\n");
|
|
|
|
}
|
|
|
|
te.N = 20;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.pfn = currState->l1Desc.pfn();
|
2010-06-02 19:58:16 +02:00
|
|
|
te.size = (1<<te.N) - 1;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.global = !currState->l1Desc.global();
|
2010-06-02 19:58:16 +02:00
|
|
|
te.valid = true;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.vpn = currState->vaddr >> te.N;
|
2010-06-02 19:58:16 +02:00
|
|
|
te.sNp = true;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.xn = currState->l1Desc.xn();
|
|
|
|
te.ap = currState->l1Desc.ap();
|
|
|
|
te.domain = currState->l1Desc.domain();
|
|
|
|
te.asid = currState->contextId;
|
|
|
|
memAttrs(currState->tc, te, currState->sctlr,
|
|
|
|
currState->l1Desc.texcb(), currState->l1Desc.shareable());
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
DPRINTF(TLB, "Inserting Section Descriptor into TLB\n");
|
2010-08-23 18:18:39 +02:00
|
|
|
DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n",
|
2010-06-02 19:58:16 +02:00
|
|
|
te.N, te.pfn, te.size, te.global, te.valid);
|
2010-08-23 18:18:39 +02:00
|
|
|
DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n",
|
|
|
|
te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid,
|
|
|
|
te.nonCacheable);
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n",
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->l1Desc.domain(), currState->l1Desc.data,
|
|
|
|
(currState->l1Desc.data >> 5) & 0xF );
|
2010-06-02 19:58:16 +02:00
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (!currState->timing) {
|
|
|
|
currState->tc = NULL;
|
|
|
|
currState->req = NULL;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
tlb->insert(currState->vaddr, te);
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
return;
|
|
|
|
case L1Descriptor::PageTable:
|
|
|
|
Addr l2desc_addr;
|
2010-06-02 19:58:18 +02:00
|
|
|
l2desc_addr = currState->l1Desc.l2Addr() |
|
|
|
|
(bits(currState->vaddr, 19,12) << 2);
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n",
|
|
|
|
l2desc_addr);
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
// Trickbox address check
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr,
|
|
|
|
sizeof(uint32_t), currState->isFetch, currState->isWrite,
|
|
|
|
currState->l1Desc.domain(), false);
|
|
|
|
|
|
|
|
if (currState->fault) {
|
|
|
|
if (!currState->timing) {
|
|
|
|
currState->tc = NULL;
|
|
|
|
currState->req = NULL;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
|
|
|
return;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->timing) {
|
|
|
|
currState->delayed = true;
|
2012-02-24 17:43:53 +01:00
|
|
|
port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
|
2012-08-28 20:30:33 +02:00
|
|
|
&doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
|
|
|
|
currState->tc->getCpuPtr()->clockPeriod());
|
2012-01-31 16:46:03 +01:00
|
|
|
} else if (!currState->functional) {
|
2012-02-24 17:43:53 +01:00
|
|
|
port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
|
2012-08-28 20:30:33 +02:00
|
|
|
NULL, (uint8_t*)&currState->l2Desc.data,
|
|
|
|
currState->tc->getCpuPtr()->clockPeriod());
|
2010-06-02 19:58:16 +02:00
|
|
|
doL2Descriptor();
|
2012-01-31 16:46:03 +01:00
|
|
|
} else {
|
MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
|
|
|
RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
|
|
|
|
masterId);
|
|
|
|
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
|
2012-01-31 16:46:03 +01:00
|
|
|
pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
|
2012-02-24 17:43:53 +01:00
|
|
|
port.sendFunctional(pkt);
|
2012-01-31 16:46:03 +01:00
|
|
|
doL2Descriptor();
|
|
|
|
delete req;
|
|
|
|
delete pkt;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
panic("A new type in a 2 bit field?\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TableWalker::doL2Descriptor()
|
|
|
|
{
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
|
|
|
|
currState->vaddr, currState->l2Desc.data);
|
2010-06-02 19:58:16 +02:00
|
|
|
TlbEntry te;
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->l2Desc.invalid()) {
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
|
2011-02-12 01:29:35 +01:00
|
|
|
if (!currState->timing) {
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->tc = NULL;
|
|
|
|
currState->req = NULL;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->isFetch)
|
|
|
|
currState->fault =
|
|
|
|
new PrefetchAbort(currState->vaddr, ArmFault::Translation1);
|
2010-06-02 19:58:16 +02:00
|
|
|
else
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->fault =
|
|
|
|
new DataAbort(currState->vaddr, currState->l1Desc.domain(),
|
|
|
|
currState->isWrite, ArmFault::Translation1);
|
2010-06-02 19:58:16 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) {
|
2010-06-02 19:58:18 +02:00
|
|
|
/** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled
|
|
|
|
* if set, do l2.Desc.setAp0() instead of generating AccessFlag0
|
|
|
|
*/
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->fault =
|
2010-08-23 18:18:39 +02:00
|
|
|
new DataAbort(currState->vaddr, 0, currState->isWrite,
|
2010-06-02 19:58:18 +02:00
|
|
|
ArmFault::AccessFlag1);
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->l2Desc.large()) {
|
2010-06-02 19:58:16 +02:00
|
|
|
te.N = 16;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.pfn = currState->l2Desc.pfn();
|
2010-06-02 19:58:16 +02:00
|
|
|
} else {
|
|
|
|
te.N = 12;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.pfn = currState->l2Desc.pfn();
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
te.valid = true;
|
|
|
|
te.size = (1 << te.N) - 1;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.asid = currState->contextId;
|
2010-06-02 19:58:16 +02:00
|
|
|
te.sNp = false;
|
2010-06-02 19:58:18 +02:00
|
|
|
te.vpn = currState->vaddr >> te.N;
|
|
|
|
te.global = currState->l2Desc.global();
|
|
|
|
te.xn = currState->l2Desc.xn();
|
|
|
|
te.ap = currState->l2Desc.ap();
|
|
|
|
te.domain = currState->l1Desc.domain();
|
|
|
|
memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(),
|
|
|
|
currState->l2Desc.shareable());
|
|
|
|
|
2011-02-12 01:29:35 +01:00
|
|
|
if (!currState->timing) {
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->tc = NULL;
|
|
|
|
currState->req = NULL;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
tlb->insert(currState->vaddr, te);
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
void
|
|
|
|
TableWalker::doL1DescriptorWrapper()
|
|
|
|
{
|
2010-08-26 02:10:43 +02:00
|
|
|
currState = stateQueueL1.front();
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->delayed = false;
|
2010-06-02 19:58:18 +02:00
|
|
|
|
2010-08-23 18:18:39 +02:00
|
|
|
DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
|
|
|
|
DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr);
|
2010-06-02 19:58:18 +02:00
|
|
|
doL1Descriptor();
|
|
|
|
|
2010-08-26 02:10:43 +02:00
|
|
|
stateQueueL1.pop_front();
|
2012-08-15 16:38:08 +02:00
|
|
|
completeDrain();
|
2010-06-02 19:58:18 +02:00
|
|
|
// Check if fault was generated
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->fault != NoFault) {
|
|
|
|
currState->transState->finish(currState->fault, currState->req,
|
|
|
|
currState->tc, currState->mode);
|
2010-06-02 19:58:18 +02:00
|
|
|
|
2010-11-08 20:58:24 +01:00
|
|
|
pending = false;
|
|
|
|
nextWalk(currState->tc);
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->req = NULL;
|
|
|
|
currState->tc = NULL;
|
|
|
|
currState->delayed = false;
|
2011-08-19 22:08:05 +02:00
|
|
|
delete currState;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
else if (!currState->delayed) {
|
2010-08-26 02:10:43 +02:00
|
|
|
// delay is not set so there is no L2 to do
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLBVerbose, "calling translateTiming again\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->fault = tlb->translateTiming(currState->req, currState->tc,
|
|
|
|
currState->transState, currState->mode);
|
|
|
|
|
2010-11-08 20:58:24 +01:00
|
|
|
pending = false;
|
|
|
|
nextWalk(currState->tc);
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->req = NULL;
|
|
|
|
currState->tc = NULL;
|
|
|
|
currState->delayed = false;
|
2010-08-26 02:10:43 +02:00
|
|
|
delete currState;
|
|
|
|
} else {
|
|
|
|
// need to do L2 descriptor
|
|
|
|
stateQueueL2.push_back(currState);
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
currState = NULL;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TableWalker::doL2DescriptorWrapper()
|
|
|
|
{
|
2010-08-26 02:10:43 +02:00
|
|
|
currState = stateQueueL2.front();
|
2010-06-02 19:58:18 +02:00
|
|
|
assert(currState->delayed);
|
2010-06-02 19:58:18 +02:00
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n",
|
|
|
|
currState->vaddr);
|
2010-06-02 19:58:18 +02:00
|
|
|
doL2Descriptor();
|
|
|
|
|
|
|
|
// Check if fault was generated
|
2010-06-02 19:58:18 +02:00
|
|
|
if (currState->fault != NoFault) {
|
|
|
|
currState->transState->finish(currState->fault, currState->req,
|
|
|
|
currState->tc, currState->mode);
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
|
|
|
else {
|
|
|
|
DPRINTF(TLBVerbose, "calling translateTiming again\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->fault = tlb->translateTiming(currState->req, currState->tc,
|
|
|
|
currState->transState, currState->mode);
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
|
|
|
|
2010-11-08 20:58:24 +01:00
|
|
|
|
|
|
|
stateQueueL2.pop_front();
|
2012-08-15 16:38:08 +02:00
|
|
|
completeDrain();
|
2010-11-08 20:58:24 +01:00
|
|
|
pending = false;
|
|
|
|
nextWalk(currState->tc);
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
currState->req = NULL;
|
|
|
|
currState->tc = NULL;
|
|
|
|
currState->delayed = false;
|
|
|
|
|
2010-08-26 02:10:43 +02:00
|
|
|
delete currState;
|
2010-06-02 19:58:18 +02:00
|
|
|
currState = NULL;
|
2010-06-02 19:58:18 +02:00
|
|
|
}
|
|
|
|
|
2010-11-08 20:58:24 +01:00
|
|
|
void
|
|
|
|
TableWalker::nextWalk(ThreadContext *tc)
|
|
|
|
{
|
|
|
|
if (pendingQueue.size())
|
2012-08-28 20:30:33 +02:00
|
|
|
schedule(doProcessEvent, tc->getCpuPtr()->clockEdge(Cycles(1)));
|
2010-11-08 20:58:24 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2010-06-02 19:58:16 +02:00
|
|
|
ArmISA::TableWalker *
|
|
|
|
ArmTableWalkerParams::create()
|
|
|
|
{
|
|
|
|
return new ArmISA::TableWalker(this);
|
|
|
|
}
|
|
|
|
|