2010-06-02 19:58:16 +02:00
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include "arch/arm/faults.hh"
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "dev/io_device.hh"
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#include "cpu/thread_context.hh"
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using namespace ArmISA;
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TableWalker::TableWalker(const Params *p)
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: MemObject(p), port(NULL), tlb(NULL), tc(NULL), req(NULL),
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doL1DescEvent(this), doL2DescEvent(this)
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{}
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TableWalker::~TableWalker()
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{
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;
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}
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unsigned int
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drain(Event *de)
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{
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panic("Not implemented\n");
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}
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Port*
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TableWalker::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "port") {
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if (port != NULL)
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fatal("%s: port already connected to %s",
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name(), port->getPeer()->name());
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System *sys = params()->sys;
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Tick minb = params()->min_backoff;
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Tick maxb = params()->max_backoff;
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port = new DmaPort(this, sys, minb, maxb);
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return port;
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}
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return NULL;
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}
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Fault
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2010-06-02 19:58:18 +02:00
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TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode,
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2010-06-02 19:58:16 +02:00
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TLB::Translation *_trans, bool _timing)
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{
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// Right now 1 CPU == 1 TLB == 1 TLB walker
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// In the future we might want to change this as multiple
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// threads/contexts could share a walker and/or a TLB
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if (tc || req)
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panic("Overlapping TLB walks attempted\n");
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tc = _tc;
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transState = _trans;
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req = _req;
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fault = NoFault;
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contextId = _cid;
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timing = _timing;
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2010-06-02 19:58:18 +02:00
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mode = _mode;
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2010-06-02 19:58:16 +02:00
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2010-06-02 19:58:18 +02:00
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/** @todo These should be cached or grabbed from cached copies in
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the TLB, all these miscreg reads are expensive */
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2010-06-02 19:58:16 +02:00
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vaddr = req->getVaddr() & ~PcModeMask;
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sctlr = tc->readMiscReg(MISCREG_SCTLR);
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cpsr = tc->readMiscReg(MISCREG_CPSR);
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N = tc->readMiscReg(MISCREG_TTBCR);
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Addr ttbr = 0;
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isFetch = (mode == TLB::Execute);
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isWrite = (mode == TLB::Write);
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isPriv = (cpsr.mode != MODE_USER);
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// If translation isn't enabled, we shouldn't be here
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assert(sctlr.m);
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2010-06-02 19:58:16 +02:00
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DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n",
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vaddr, N, mbits(vaddr, 31, 32-N));
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if (N == 0 || !mbits(vaddr, 31, 32-N)) {
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DPRINTF(TLB, " - Selecting TTBR0\n");
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2010-06-02 19:58:16 +02:00
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ttbr = tc->readMiscReg(MISCREG_TTBR0);
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} else {
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2010-06-02 19:58:16 +02:00
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DPRINTF(TLB, " - Selecting TTBR1\n");
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ttbr = tc->readMiscReg(MISCREG_TTBR1);
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2010-06-02 19:58:16 +02:00
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N = 0;
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}
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Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(vaddr,31-N,20) << 2);
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2010-06-02 19:58:16 +02:00
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DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr);
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2010-06-02 19:58:16 +02:00
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// Trickbox address check
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fault = tlb->walkTrickBoxCheck(l1desc_addr, vaddr, sizeof(uint32_t),
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2010-06-02 19:58:16 +02:00
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isFetch, isWrite, 0, true);
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2010-06-02 19:58:16 +02:00
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if (fault) {
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tc = NULL;
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req = NULL;
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return fault;
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}
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if (timing) {
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port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
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&doL1DescEvent, (uint8_t*)&l1Desc.data, (Tick)0);
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} else {
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port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
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NULL, (uint8_t*)&l1Desc.data, (Tick)0);
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doL1Descriptor();
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}
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return fault;
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}
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void
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2010-06-02 19:58:18 +02:00
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TableWalker::memAttrs(TlbEntry &te, uint8_t texcb, bool s)
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2010-06-02 19:58:16 +02:00
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{
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2010-06-02 19:58:18 +02:00
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DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s);
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te.shareable = false; // default value
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bool outer_shareable = false;
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2010-06-02 19:58:16 +02:00
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if (sctlr.tre == 0) {
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switch(texcb) {
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2010-06-02 19:58:18 +02:00
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case 0: // Stongly-ordered
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te.nonCacheable = true;
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te.mtype = TlbEntry::StronglyOrdered;
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te.shareable = true;
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te.innerAttrs = 1;
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te.outerAttrs = 0;
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break;
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case 1: // Shareable Device
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2010-06-02 19:58:16 +02:00
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te.nonCacheable = true;
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2010-06-02 19:58:18 +02:00
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te.mtype = TlbEntry::Device;
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te.shareable = true;
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te.innerAttrs = 3;
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te.outerAttrs = 0;
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break;
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case 2: // Outer and Inner Write-Through, no Write-Allocate
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 6;
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te.outerAttrs = bits(texcb, 1, 0);
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break;
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case 3: // Outer and Inner Write-Back, no Write-Allocate
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 7;
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te.outerAttrs = bits(texcb, 1, 0);
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break;
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case 4: // Outer and Inner Non-cacheable
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te.nonCacheable = true;
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 0;
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te.outerAttrs = bits(texcb, 1, 0);
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break;
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case 5: // Reserved
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break;
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case 6: // Implementation Defined
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2010-06-02 19:58:16 +02:00
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break;
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2010-06-02 19:58:18 +02:00
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case 7: // Outer and Inner Write-Back, Write-Allocate
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 5;
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te.outerAttrs = 1;
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break;
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case 8: // Non-shareable Device
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te.nonCacheable = true;
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te.mtype = TlbEntry::Device;
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te.shareable = false;
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te.innerAttrs = 3;
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te.outerAttrs = 0;
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break;
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case 9 ... 15: // Reserved
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break;
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case 16 ... 31: // Cacheable Memory
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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2010-06-02 19:58:16 +02:00
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if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0)
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te.nonCacheable = true;
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2010-06-02 19:58:18 +02:00
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te.innerAttrs = bits(texcb, 1, 0);
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te.outerAttrs = bits(texcb, 3, 2);
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2010-06-02 19:58:16 +02:00
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break;
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2010-06-02 19:58:18 +02:00
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default:
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panic("More than 32 states for 5 bits?\n");
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2010-06-02 19:58:16 +02:00
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}
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} else {
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PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
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NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
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2010-06-02 19:58:18 +02:00
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DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
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uint8_t curr_tr, curr_ir, curr_or;
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2010-06-02 19:58:16 +02:00
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switch(bits(texcb, 2,0)) {
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case 0:
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2010-06-02 19:58:18 +02:00
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curr_tr = prrr.tr0;
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curr_ir = nmrr.ir0;
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curr_or = nmrr.or0;
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outer_shareable = (prrr.nos0 == 0);
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2010-06-02 19:58:16 +02:00
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break;
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case 1:
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2010-06-02 19:58:18 +02:00
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curr_tr = prrr.tr1;
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curr_ir = nmrr.ir1;
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curr_or = nmrr.or1;
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outer_shareable = (prrr.nos1 == 0);
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2010-06-02 19:58:16 +02:00
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break;
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case 2:
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2010-06-02 19:58:18 +02:00
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curr_tr = prrr.tr2;
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curr_ir = nmrr.ir2;
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curr_or = nmrr.or2;
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outer_shareable = (prrr.nos2 == 0);
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2010-06-02 19:58:16 +02:00
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break;
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case 3:
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2010-06-02 19:58:18 +02:00
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curr_tr = prrr.tr3;
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curr_ir = nmrr.ir3;
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curr_or = nmrr.or3;
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outer_shareable = (prrr.nos3 == 0);
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2010-06-02 19:58:16 +02:00
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break;
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case 4:
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2010-06-02 19:58:18 +02:00
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curr_tr = prrr.tr4;
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curr_ir = nmrr.ir4;
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curr_or = nmrr.or4;
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outer_shareable = (prrr.nos4 == 0);
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2010-06-02 19:58:16 +02:00
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break;
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case 5:
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2010-06-02 19:58:18 +02:00
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curr_tr = prrr.tr5;
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curr_ir = nmrr.ir5;
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curr_or = nmrr.or5;
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outer_shareable = (prrr.nos5 == 0);
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2010-06-02 19:58:16 +02:00
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break;
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case 6:
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panic("Imp defined type\n");
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case 7:
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2010-06-02 19:58:18 +02:00
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curr_tr = prrr.tr7;
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curr_ir = nmrr.ir7;
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curr_or = nmrr.or7;
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outer_shareable = (prrr.nos7 == 0);
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2010-06-02 19:58:16 +02:00
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break;
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}
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2010-06-02 19:58:18 +02:00
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switch(curr_tr) {
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case 0:
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DPRINTF(TLBVerbose, "StronglyOrdered\n");
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te.mtype = TlbEntry::StronglyOrdered;
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te.nonCacheable = true;
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te.innerAttrs = 1;
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te.outerAttrs = 0;
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te.shareable = true;
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break;
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case 1:
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DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n",
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prrr.ds1, prrr.ds0, s);
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te.mtype = TlbEntry::Device;
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te.nonCacheable = true;
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te.innerAttrs = 3;
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te.outerAttrs = 0;
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if (prrr.ds1 && s)
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te.shareable = true;
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if (prrr.ds0 && !s)
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te.shareable = true;
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break;
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case 2:
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DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n",
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prrr.ns1, prrr.ns0, s);
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te.mtype = TlbEntry::Normal;
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if (prrr.ns1 && s)
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te.shareable = true;
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if (prrr.ns0 && !s)
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te.shareable = true;
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//te.shareable = outer_shareable;
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break;
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case 3:
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panic("Reserved type");
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}
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if (te.mtype == TlbEntry::Normal){
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switch(curr_ir) {
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case 0:
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te.nonCacheable = true;
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te.innerAttrs = 0;
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break;
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case 1:
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te.innerAttrs = 5;
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break;
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case 2:
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te.innerAttrs = 6;
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break;
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case 3:
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te.innerAttrs = 7;
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break;
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}
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switch(curr_or) {
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case 0:
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te.nonCacheable = true;
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te.outerAttrs = 0;
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break;
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|
|
|
case 1:
|
|
|
|
te.outerAttrs = 1;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
te.outerAttrs = 2;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
te.outerAttrs = 3;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
2010-06-02 19:58:18 +02:00
|
|
|
|
|
|
|
/** Formatting for Physical Address Register (PAR)
|
|
|
|
* Only including lower bits (TLB info here)
|
|
|
|
* PAR:
|
|
|
|
* PA [31:12]
|
|
|
|
* Reserved [11]
|
|
|
|
* TLB info [10:1]
|
|
|
|
* NOS [10] (Not Outer Sharable)
|
|
|
|
* NS [9] (Non-Secure)
|
|
|
|
* -- [8] (Implementation Defined)
|
|
|
|
* SH [7] (Sharable)
|
|
|
|
* Inner[6:4](Inner memory attributes)
|
|
|
|
* Outer[3:2](Outer memory attributes)
|
|
|
|
* SS [1] (SuperSection)
|
|
|
|
* F [0] (Fault, Fault Status in [6:1] if faulted)
|
|
|
|
*/
|
|
|
|
te.attributes = (
|
|
|
|
((outer_shareable ? 0:1) << 10) |
|
|
|
|
// TODO: NS Bit
|
|
|
|
((te.shareable ? 1:0) << 7) |
|
|
|
|
(te.innerAttrs << 4) |
|
|
|
|
(te.outerAttrs << 2)
|
|
|
|
// TODO: Supersection bit
|
|
|
|
// TODO: Fault bit
|
|
|
|
);
|
|
|
|
|
|
|
|
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TableWalker::doL1Descriptor()
|
|
|
|
{
|
|
|
|
DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", vaddr, l1Desc.data);
|
|
|
|
TlbEntry te;
|
|
|
|
|
|
|
|
switch (l1Desc.type()) {
|
|
|
|
case L1Descriptor::Ignore:
|
|
|
|
case L1Descriptor::Reserved:
|
2010-06-02 19:58:18 +02:00
|
|
|
if (!delayed) {
|
|
|
|
tc = NULL;
|
|
|
|
req = NULL;
|
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
|
|
|
|
if (isFetch)
|
|
|
|
fault = new PrefetchAbort(vaddr, ArmFault::Translation0);
|
|
|
|
else
|
2010-06-02 19:58:18 +02:00
|
|
|
fault = new DataAbort(vaddr, NULL, isWrite,
|
|
|
|
ArmFault::Translation0);
|
2010-06-02 19:58:16 +02:00
|
|
|
return;
|
|
|
|
case L1Descriptor::Section:
|
2010-06-02 19:58:18 +02:00
|
|
|
if (sctlr.afe && bits(l1Desc.ap(), 0) == 0) {
|
|
|
|
/** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is
|
|
|
|
* enabled if set, do l1.Desc.setAp0() instead of generating
|
|
|
|
* AccessFlag0
|
|
|
|
*/
|
|
|
|
|
|
|
|
fault = new DataAbort(vaddr, NULL, isWrite,
|
|
|
|
ArmFault::AccessFlag0);
|
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
if (l1Desc.supersection()) {
|
|
|
|
panic("Haven't implemented supersections\n");
|
|
|
|
}
|
|
|
|
te.N = 20;
|
|
|
|
te.pfn = l1Desc.pfn();
|
|
|
|
te.size = (1<<te.N) - 1;
|
|
|
|
te.global = !l1Desc.global();
|
|
|
|
te.valid = true;
|
|
|
|
te.vpn = vaddr >> te.N;
|
|
|
|
te.sNp = true;
|
|
|
|
te.xn = l1Desc.xn();
|
|
|
|
te.ap = l1Desc.ap();
|
|
|
|
te.domain = l1Desc.domain();
|
|
|
|
te.asid = contextId;
|
2010-06-02 19:58:18 +02:00
|
|
|
memAttrs(te, l1Desc.texcb(), l1Desc.shareable());
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
DPRINTF(TLB, "Inserting Section Descriptor into TLB\n");
|
|
|
|
DPRINTF(TLB, " - N%d pfn:%#x size: %#x global:%d valid: %d\n",
|
|
|
|
te.N, te.pfn, te.size, te.global, te.valid);
|
|
|
|
DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d\n",
|
|
|
|
te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid);
|
|
|
|
DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n",
|
|
|
|
l1Desc.domain(), l1Desc.data, (l1Desc.data >> 5) & 0xF );
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (!timing) {
|
|
|
|
tc = NULL;
|
|
|
|
req = NULL;
|
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
tlb->insert(vaddr, te);
|
|
|
|
|
|
|
|
return;
|
|
|
|
case L1Descriptor::PageTable:
|
|
|
|
Addr l2desc_addr;
|
|
|
|
l2desc_addr = l1Desc.l2Addr() | (bits(vaddr, 19,12) << 2);
|
2010-06-02 19:58:18 +02:00
|
|
|
DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n",
|
|
|
|
l2desc_addr);
|
2010-06-02 19:58:16 +02:00
|
|
|
|
|
|
|
// Trickbox address check
|
|
|
|
fault = tlb->walkTrickBoxCheck(l2desc_addr, vaddr, sizeof(uint32_t),
|
2010-06-02 19:58:16 +02:00
|
|
|
isFetch, isWrite, l1Desc.domain(), false);
|
2010-06-02 19:58:16 +02:00
|
|
|
if (fault) {
|
2010-06-02 19:58:18 +02:00
|
|
|
if (!timing) {
|
|
|
|
tc = NULL;
|
|
|
|
req = NULL;
|
|
|
|
}
|
|
|
|
return;
|
2010-06-02 19:58:16 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (timing) {
|
2010-06-02 19:58:18 +02:00
|
|
|
delayed = true;
|
2010-06-02 19:58:16 +02:00
|
|
|
port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
|
|
|
|
&doL2DescEvent, (uint8_t*)&l2Desc.data, 0);
|
|
|
|
} else {
|
|
|
|
port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
|
|
|
|
NULL, (uint8_t*)&l2Desc.data, 0);
|
|
|
|
doL2Descriptor();
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
panic("A new type in a 2 bit field?\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TableWalker::doL2Descriptor()
|
|
|
|
{
|
|
|
|
DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", vaddr, l2Desc.data);
|
|
|
|
TlbEntry te;
|
|
|
|
|
|
|
|
if (l2Desc.invalid()) {
|
|
|
|
DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
|
2010-06-02 19:58:18 +02:00
|
|
|
if (!delayed) {
|
|
|
|
tc = NULL;
|
|
|
|
req = NULL;
|
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
if (isFetch)
|
|
|
|
fault = new PrefetchAbort(vaddr, ArmFault::Translation1);
|
|
|
|
else
|
2010-06-02 19:58:18 +02:00
|
|
|
fault = new DataAbort(vaddr, l1Desc.domain(), isWrite,
|
|
|
|
ArmFault::Translation1);
|
2010-06-02 19:58:16 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (sctlr.afe && bits(l2Desc.ap(), 0) == 0) {
|
|
|
|
/** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled
|
|
|
|
* if set, do l2.Desc.setAp0() instead of generating AccessFlag0
|
|
|
|
*/
|
|
|
|
|
|
|
|
fault = new DataAbort(vaddr, NULL, isWrite, ArmFault::AccessFlag1);
|
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:16 +02:00
|
|
|
if (l2Desc.large()) {
|
|
|
|
te.N = 16;
|
|
|
|
te.pfn = l2Desc.pfn();
|
|
|
|
} else {
|
|
|
|
te.N = 12;
|
|
|
|
te.pfn = l2Desc.pfn();
|
|
|
|
}
|
|
|
|
|
|
|
|
te.valid = true;
|
|
|
|
te.size = (1 << te.N) - 1;
|
|
|
|
te.asid = contextId;
|
|
|
|
te.sNp = false;
|
|
|
|
te.vpn = vaddr >> te.N;
|
|
|
|
te.global = l2Desc.global();
|
|
|
|
te.xn = l2Desc.xn();
|
|
|
|
te.ap = l2Desc.ap();
|
|
|
|
te.domain = l1Desc.domain();
|
2010-06-02 19:58:18 +02:00
|
|
|
memAttrs(te, l2Desc.texcb(), l2Desc.shareable());
|
2010-06-02 19:58:16 +02:00
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
if (!delayed) {
|
|
|
|
tc = NULL;
|
|
|
|
req = NULL;
|
|
|
|
}
|
2010-06-02 19:58:16 +02:00
|
|
|
tlb->insert(vaddr, te);
|
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:18 +02:00
|
|
|
void
|
|
|
|
TableWalker::doL1DescriptorWrapper()
|
|
|
|
{
|
|
|
|
delayed = false;
|
|
|
|
|
|
|
|
DPRINTF(TLBVerbose, "calling doL1Descriptor\n");
|
|
|
|
doL1Descriptor();
|
|
|
|
|
|
|
|
// Check if fault was generated
|
|
|
|
if (fault != NoFault) {
|
|
|
|
transState->finish(fault, req, tc, mode);
|
|
|
|
|
|
|
|
req = NULL;
|
|
|
|
tc = NULL;
|
|
|
|
delayed = false;
|
|
|
|
}
|
|
|
|
else if (!delayed) {
|
|
|
|
DPRINTF(TLBVerbose, "calling translateTiming again\n");
|
|
|
|
fault = tlb->translateTiming(req, tc, transState, mode);
|
|
|
|
|
|
|
|
req = NULL;
|
|
|
|
tc = NULL;
|
|
|
|
delayed = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TableWalker::doL2DescriptorWrapper()
|
|
|
|
{
|
|
|
|
assert(delayed);
|
|
|
|
|
|
|
|
DPRINTF(TLBVerbose, "calling doL2Descriptor\n");
|
|
|
|
doL2Descriptor();
|
|
|
|
|
|
|
|
// Check if fault was generated
|
|
|
|
if (fault != NoFault) {
|
|
|
|
transState->finish(fault, req, tc, mode);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
DPRINTF(TLBVerbose, "calling translateTiming again\n");
|
|
|
|
fault = tlb->translateTiming(req, tc, transState, mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
req = NULL;
|
|
|
|
tc = NULL;
|
|
|
|
delayed = false;
|
|
|
|
}
|
|
|
|
|
2010-06-02 19:58:16 +02:00
|
|
|
ArmISA::TableWalker *
|
|
|
|
ArmTableWalkerParams::create()
|
|
|
|
{
|
|
|
|
return new ArmISA::TableWalker(this);
|
|
|
|
}
|
|
|
|
|