2011-06-21 04:44:24 +02:00
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000025 # Number of seconds simulated
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2011-07-10 19:56:09 +02:00
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sim_ticks 25058500 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 25058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-06-21 04:44:24 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-02-12 23:07:43 +01:00
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host_inst_rate 93467 # Simulator instruction rate (inst/s)
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host_op_rate 93457 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 154309649 # Simulator tick rate (ticks/s)
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host_mem_usage 211048 # Number of bytes of host memory used
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host_seconds 0.16 # Real time elapsed on the host
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2011-06-21 04:44:24 +02:00
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sim_insts 15175 # Number of instructions simulated
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2012-02-12 23:07:43 +01:00
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sim_ops 15175 # Number of ops (including micro ops) simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 27904 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 19072 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 436 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 1113554283 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 761099028 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 1113554283 # Total bandwidth to/from this memory (bytes/s)
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2011-06-21 04:44:24 +02:00
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system.cpu.workload.num_syscalls 18 # Number of system calls
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2011-07-10 19:56:09 +02:00
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system.cpu.numCycles 50118 # number of cpu cycles simulated
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2011-06-21 04:44:24 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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2011-07-10 19:56:09 +02:00
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system.cpu.threadCycles 21993 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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2011-06-21 04:44:24 +02:00
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself
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2011-07-10 19:56:09 +02:00
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system.cpu.idleCycles 32493 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 17625 # Number of cycles cpu stages are processed.
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system.cpu.activity 35.167006 # Percentage of cycles cpu is active
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2011-06-21 04:44:24 +02:00
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system.cpu.comLoads 2226 # Number of Load instructions committed
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system.cpu.comStores 1448 # Number of Store instructions committed
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system.cpu.comBranches 3359 # Number of Branches instructions committed
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system.cpu.comNops 726 # Number of Nop instructions committed
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system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed
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system.cpu.comInts 7177 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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2012-02-12 23:07:43 +01:00
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system.cpu.committedInsts 15175 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread)
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2011-06-21 04:44:24 +02:00
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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2011-07-10 19:56:09 +02:00
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system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.302785 # IPC: Instructions Per Cycle (Per-Thread)
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2011-06-21 04:44:24 +02:00
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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2011-07-10 19:56:09 +02:00
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system.cpu.ipc_total 0.302785 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 5166 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 3601 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 2377 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 4346 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 2912 # Number of BTB hits
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2011-06-21 04:44:24 +02:00
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system.cpu.branch_predictor.usedRAS 172 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
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2011-07-10 19:56:09 +02:00
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system.cpu.branch_predictor.BTBHitPct 67.004142 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 3084 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 2082 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 14334 # Number of Reads from Int. Register File
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2011-06-21 04:44:24 +02:00
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system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File
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2011-07-10 19:56:09 +02:00
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system.cpu.regfile_manager.intRegFileAccesses 25445 # Total Accesses (Read+Write) to the Int. Register File
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2011-06-21 04:44:24 +02:00
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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2011-07-10 19:56:09 +02:00
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system.cpu.regfile_manager.regForwards 5192 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 3845 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 1598 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 716 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 2314 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 1045 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 68.889550 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 11051 # Number of Instructions Executed.
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2011-06-21 04:44:24 +02:00
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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2011-07-10 19:56:09 +02:00
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system.cpu.stage0.idleCycles 36528 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 13590 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 27.116006 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 40773 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 9345 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 18.645995 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 41295 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 8823 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 17.604453 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 47234 # Number of cycles 0 instructions are processed.
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2011-06-21 04:44:24 +02:00
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system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
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2011-07-10 19:56:09 +02:00
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system.cpu.stage3.utilization 5.754420 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 40795 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 9323 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 18.602099 # Percentage of cycles stage was utilized (processing insts).
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2011-06-21 04:44:24 +02:00
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system.cpu.icache.replacements 0 # number of replacements
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.tagsinuse 165.645515 # Cycle average of tags in use
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system.cpu.icache.total_refs 3085 # Total number of references to valid blocks.
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2011-06-21 04:44:24 +02:00
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system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
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2011-07-10 19:56:09 +02:00
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system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks.
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2011-06-21 04:44:24 +02:00
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.occ_blocks::cpu.inst 165.645515 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.080882 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.080882 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 3085 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 3085 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 3085 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 3085 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 3085 # number of overall hits
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system.cpu.icache.overall_hits::total 3085 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
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system.cpu.icache.overall_misses::total 366 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 20100000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 20100000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 20100000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 20100000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 20100000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 20100000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 3451 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 3451 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 3451 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 3451 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 3451 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 3451 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.106056 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.106056 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.106056 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54918.032787 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency
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2011-06-21 04:44:24 +02:00
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2012-02-12 23:07:43 +01:00
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15872000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 15872000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
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2011-06-21 04:44:24 +02:00
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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2011-07-10 19:56:09 +02:00
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system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use
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2011-06-21 04:44:24 +02:00
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system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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system.cpu.dcache.occ_blocks::cpu.data 97.082868 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.023702 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.023702 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 1142 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 1142 # number of WriteReq hits
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system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
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system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
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system.cpu.dcache.demand_hits::cpu.data 3310 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 3310 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 3310 # number of overall hits
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system.cpu.dcache.overall_hits::total 3310 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 300 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 300 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
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|
|
system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 358 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3282500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16398000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 16398000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 19680500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 19680500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 19680500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 19680500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56594.827586 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54660 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 44 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 215 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 215 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 220 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 220 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 220 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2838000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2838000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4545000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4545000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53547.169811 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 165.036640 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31.270807 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.005037 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.005991 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15533000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2777500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18310500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4442500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4442500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 15533000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7220000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 15533000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7220000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52405.660377 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2132500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14048500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3416000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3416000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17464500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
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2011-06-21 04:44:24 +02:00
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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---------- End Simulation Statistics ----------
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