2007-06-22 21:06:10 +02:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.424846 # Number of seconds simulated
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sim_ticks 424846003000 # Number of ticks simulated
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2007-06-22 21:06:10 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 130905 # Simulator instruction rate (inst/s)
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host_tick_rate 39566335 # Simulator tick rate (ticks/s)
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host_mem_usage 260032 # Number of bytes of host memory used
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host_seconds 10737.56 # Real time elapsed on the host
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2010-10-31 08:07:48 +01:00
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sim_insts 1405604152 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 49 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 849692007 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 103951242 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 92817618 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 5441892 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 101027131 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 99845588 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.usedRAS 1240 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 176461208 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1731297968 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 103951242 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 99846828 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 372380430 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 32542357 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 273950532 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 1598 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 171982366 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1072419 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 849334249 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.043796 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.987927 # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 476953819 56.16% 56.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 82874443 9.76% 65.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 45104012 5.31% 71.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 23823207 2.80% 74.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 33449263 3.94% 77.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 34018296 4.01% 81.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 14934889 1.76% 83.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 7594649 0.89% 84.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 130581671 15.37% 100.00% # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 849334249 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.122340 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.037559 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 228750775 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 225010682 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 340329593 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 28702732 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 26540467 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 1719853048 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 26540467 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 263479088 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 41404306 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 55665718 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 333164025 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 129080645 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 1702621917 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 27946870 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 65424391 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 16478266 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 1420563184 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 2876973295 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 2842990293 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 33983002 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed
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2011-08-19 22:08:08 +02:00
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system.cpu.rename.UndoneMaps 175792732 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 3237844 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 3287220 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 297721307 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 456905033 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 186186881 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 277685429 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 94682535 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 1573041480 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 3078086 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1493571680 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 168879 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 169173312 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 193746620 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 834415 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 849334249 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.758520 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.350284 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 177901650 20.95% 20.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 206358445 24.30% 45.24% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 226462970 26.66% 71.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 151667203 17.86% 89.76% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 64968416 7.65% 97.41% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 14273144 1.68% 99.09% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 6071046 0.71% 99.81% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 1430974 0.17% 99.98% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 200401 0.02% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 849334249 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 106837 5.02% 5.02% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 176348 8.29% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1497549 70.41% 83.72% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 346224 16.28% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::IntAlu 886788388 59.37% 59.37% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 2623578 0.18% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
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|
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
|
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
|
|
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 430759220 28.84% 88.39% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 173400494 11.61% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::total 1493571680 # Type of FU issued
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system.cpu.iq.rate 1.757780 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 2126958 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst)
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|
|
system.cpu.iq.int_inst_queue_reads 3820899737 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 1736825318 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1473365597 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 17873709 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 9212850 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 8524107 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1486479437 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 9219201 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 209970408 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 54392189 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 142413 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 763229 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 19338739 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 609 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 45345 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 26540467 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2525220 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 145175 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 1675654819 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 4255922 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 456905033 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 186186881 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 2976415 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 59600 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 9064 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 763229 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 5291175 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 468114 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 5759289 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1486215446 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 427697474 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 7356234 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_nop 99535253 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 599761085 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 90544158 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 172063611 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.749123 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1483627085 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1481889704 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1175309728 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 1225337993 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 1.744032 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.959172 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 186029259 # The number of squashed insts skipped by commit
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branchMispredicts 5441892 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 822794393 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.810323 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.360899 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 271095175 32.95% 32.95% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 302645797 36.78% 69.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 45322356 5.51% 75.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 68686908 8.35% 83.59% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 22732084 2.76% 86.35% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 9729610 1.18% 87.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 29628308 3.60% 91.13% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 10807412 1.31% 92.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 62146743 7.55% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 822794393 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.count 1489523295 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 569360986 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 402512844 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 51356 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 86248929 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 62146743 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 2436135334 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 3377694632 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 11301 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 357758 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.cpi 0.604503 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.604503 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.654251 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.654251 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 2015965671 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1304123959 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 16988422 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 10452078 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 605607850 # number of misc regfile reads
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.replacements 166 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1030.164560 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 171980565 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 132598.739399 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1030.164560 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.503010 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 171980565 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 171980565 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 171980565 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1801 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1801 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1801 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 62794000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 62794000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 62794000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 171982366 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 171982366 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 171982366 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34866.185453 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34866.185453 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34866.185453 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 503 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 503 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 503 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 45168500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 45168500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 45168500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.536210 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 475459 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4095.196777 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 381789765 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 479555 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 796.133426 # Average number of references to valid blocks.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 4095.196777 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999804 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 216852847 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 164935599 # number of WriteReq hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_hits 381788446 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 381788446 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 816608 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1911217 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_misses 2727825 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2727825 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 11966798000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 30001558232 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 41968356232 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 41968356232 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 217669455 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_accesses 384516271 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 384516271 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.003752 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.011455 # miss rate for WriteReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.007094 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.007094 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 14654.274756 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 15697.620015 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 15385.281766 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 15385.281766 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 7500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2071.428571 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 7500 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 426734 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 604334 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1643943 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 2248277 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 2248277 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 212274 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 267274 # number of WriteReq MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 479548 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 479548 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1589212000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3626989841 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 5216201841 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 5216201841 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.001247 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.001247 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7486.606933 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13570.305533 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.replacements 75834 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 17835.857801 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 464745 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 91356 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 5.087186 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2067.900619 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 15767.957182 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.063107 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.481200 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 179917 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 426734 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 206874 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 386791 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 386791 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 33655 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 60407 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 94062 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 94062 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1145507000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2078924500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 3224431500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 3224431500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 213572 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 426734 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 267281 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 480853 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 480853 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.157582 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.226006 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.195615 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.195615 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.755311 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34415.291274 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34279.852650 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34279.852650 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.writebacks 59251 # number of writebacks
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 33655 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 60407 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 94062 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 94062 # number of overall MSHR misses
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1043470000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892046500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2935516500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2935516500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157582 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226006 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.195615 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.195615 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.902689 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31321.643187 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-06-22 21:06:10 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
