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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_seconds 1.842698 # Number of seconds simulated
sim_ticks 1842697801000 # Number of ticks simulated
final_tick 1842697801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
host_inst_rate 215096 # Simulator instruction rate (inst/s)
host_op_rate 215096 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5452418287 # Simulator tick rate (ticks/s)
host_mem_usage 309280 # Number of bytes of host memory used
host_seconds 337.96 # Real time elapsed on the host
sim_insts 72693799 # Number of instructions simulated
sim_ops 72693799 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 487424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20019264 # Number of bytes read from this memory
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu1.inst 147904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2316480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 282624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2529216 # Number of bytes read from this memory
system.physmem.bytes_read::total 28435264 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 487424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 147904 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 282624 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 917952 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory
system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 312801 # Number of read requests responded to by this memory
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu1.inst 2311 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 36195 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4416 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 39519 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444301 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 264517 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10864106 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 80265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1257113 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 153375 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1372561 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15431322 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 264517 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 80265 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 153375 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498157 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4048186 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4048186 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4048186 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 264517 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10864106 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 80265 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1257113 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 153375 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1372561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19479509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 99716 # Total number of read requests seen
system.physmem.writeReqs 44920 # Total number of write requests seen
system.physmem.cpureqs 144680 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 6381824 # Total number of bytes read from memory
system.physmem.bytesWritten 2874880 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 6381824 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2874880 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 6258 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 6027 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 6219 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 6346 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 6396 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 6153 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 6072 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 6492 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 6415 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 6657 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 6000 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 6017 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 6370 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 6370 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 6146 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 2882 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 2656 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 2846 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 2961 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 2624 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 3004 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 2707 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 3214 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 2827 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 3022 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 2441 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 2472 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 2709 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 2853 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 2760 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 1841685476500 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::6 99716 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::6 44920 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 68031 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 12674 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6197 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2237 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1385 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1270 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 664 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 645 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 634 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 616 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 594 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 598 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 841 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 979 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 938 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 504 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 188 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 42 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::0 1388 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1426 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1839 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1967 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1966 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1963 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1963 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1958 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1953 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1952 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1949 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1948 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1946 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1941 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1939 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1939 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 1938 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 1934 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 1932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 1929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 621 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 554 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 15781 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 586.280717 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 172.240853 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1929.214074 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 6626 41.99% 41.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 2550 16.16% 58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 1431 9.07% 67.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 896 5.68% 72.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 638 4.04% 76.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 562 3.56% 80.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 391 2.48% 82.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 301 1.91% 84.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 260 1.65% 86.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 205 1.30% 87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 214 1.36% 89.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 213 1.35% 90.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 77 0.49% 91.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 70 0.44% 91.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 80 0.51% 91.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 90 0.57% 92.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 36 0.23% 92.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 39 0.25% 93.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 57 0.36% 93.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 48 0.30% 93.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 35 0.22% 94.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 177 1.12% 95.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 87 0.55% 95.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 34 0.22% 96.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 7 0.04% 96.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 18 0.11% 96.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 14 0.09% 96.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 8 0.05% 96.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 6 0.04% 96.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 4 0.03% 96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 1 0.01% 96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 1 0.01% 96.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 2 0.01% 96.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 1 0.01% 96.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 1 0.01% 96.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 1 0.01% 96.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 1 0.01% 96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 1 0.01% 96.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 1 0.01% 96.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 1 0.01% 96.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595 1 0.01% 96.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 1 0.01% 96.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 384 2.43% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523 1 0.01% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299 1 0.01% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 8 0.05% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195 1 0.01% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515 1 0.01% 99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707 1 0.01% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 15781 # Bytes accessed per row activation
system.physmem.totQLat 1934459750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 3605914750 # Sum of mem lat for all requests
system.physmem.totBusLat 498525000 # Total cycles spent in databus access
system.physmem.totBankLat 1172930000 # Total cycles spent in bank access
system.physmem.avgQLat 19401.83 # Average queueing delay per request
system.physmem.avgBankLat 11764.00 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgMemAccLat 36165.84 # Average memory access latency
system.physmem.avgRdBW 3.46 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.46 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.avgRdQLen 0.00 # Average read queue length over time
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.avgWrQLen 0.17 # Average write queue length over time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHits 93388 # Number of row buffer hits during reads
system.physmem.writeRowHits 35434 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.66 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.88 # Row buffer hit rate for writes
system.physmem.avgGap 12733243.98 # Average gap between requests
system.membus.throughput 19523449 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 46002 # Transaction distribution
system.membus.trans_dist::ReadResp 45972 # Transaction distribution
system.membus.trans_dist::WriteReq 3749 # Transaction distribution
system.membus.trans_dist::WriteResp 3749 # Transaction distribution
system.membus.trans_dist::Writeback 44920 # Transaction distribution
system.membus.trans_dist::UpgradeReq 46 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 47 # Transaction distribution
system.membus.trans_dist::ReadExReq 56809 # Transaction distribution
system.membus.trans_dist::ReadExResp 56809 # Transaction distribution
system.membus.trans_dist::BadAddressError 30 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13314 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 192737 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 206111 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51863 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 51863 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 13314 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 244600 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 257974 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7047808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 7063555 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208896 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2208896 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 15747 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 9256704 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 9272451 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 35965768 # Total data (bytes)
system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 12475000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 520545500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 35000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 777595953 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 156419750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.l2c.replacements 337378 # number of replacements
system.l2c.tagsinuse 65422.722236 # Cycle average of tags in use
system.l2c.total_refs 2472063 # Total number of references to valid blocks.
system.l2c.sampled_refs 402541 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.141146 # Average number of references to valid blocks.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.occ_blocks::writebacks 54907.432737 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 2460.754948 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2679.156770 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 579.419963 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 590.394247 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 2099.377178 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 2106.186392 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.837821 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.037548 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.040881 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.008841 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.009009 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.032034 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.032138 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.998272 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 520270 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 493307 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 124051 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 83977 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 292923 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 239241 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1753769 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835411 # number of Writeback hits
system.l2c.Writeback_hits::total 835411 # number of Writeback hits
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadExReq_hits::cpu0.data 92891 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 26438 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 67572 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 186901 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 520270 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 586198 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 124051 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 110415 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 292923 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 306813 # number of demand (read+write) hits
system.l2c.demand_hits::total 1940670 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 520270 # number of overall hits
system.l2c.overall_hits::cpu0.data 586198 # number of overall hits
system.l2c.overall_hits::cpu1.inst 124051 # number of overall hits
system.l2c.overall_hits::cpu1.data 110415 # number of overall hits
system.l2c.overall_hits::cpu2.inst 292923 # number of overall hits
system.l2c.overall_hits::cpu2.data 306813 # number of overall hits
system.l2c.overall_hits::total 1940670 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 7616 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 236907 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2311 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 17559 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 4416 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 18739 # number of ReadReq misses
system.l2c.ReadReq_misses::total 287548 # number of ReadReq misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_misses::cpu2.data 13 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 21 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 76169 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 18684 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 20878 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 115731 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 7616 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 313076 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2311 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 36243 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 4416 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 39617 # number of demand (read+write) misses
system.l2c.demand_misses::total 403279 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 7616 # number of overall misses
system.l2c.overall_misses::cpu0.data 313076 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2311 # number of overall misses
system.l2c.overall_misses::cpu1.data 36243 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4416 # number of overall misses
system.l2c.overall_misses::cpu2.data 39617 # number of overall misses
system.l2c.overall_misses::total 403279 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 188862500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 1140165500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 381530000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1210319500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2920877500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 285000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 285000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1218529000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1740228500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2958757500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 188862500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2358694500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 381530000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 2950548000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 5879635000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 188862500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2358694500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 381530000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 2950548000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 5879635000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 527886 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 730214 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 126362 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 101536 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 297339 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 257980 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2041317 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 835411 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835411 # number of Writeback accesses(hits+misses)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 29 # number of UpgradeReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadExReq_accesses::cpu0.data 169060 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 45122 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 88450 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 302632 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 527886 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 899274 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 126362 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 146658 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 297339 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 346430 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2343949 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 527886 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 899274 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 126362 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 146658 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 297339 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 346430 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2343949 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014427 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.324435 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.018289 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.172934 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.014852 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.072637 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.140864 # miss rate for ReadReq accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.764706 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.724138 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data 1 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.450544 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.414077 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.236043 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.382415 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014427 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.348143 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.018289 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.247126 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014852 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.114358 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.172051 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014427 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.348143 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.018289 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.247126 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014852 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.114358 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.172051 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81723.279965 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 64933.395979 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86397.192029 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 64588.265116 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 10157.877989 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 21923.076923 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 13571.428571 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 65217.779919 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83352.260753 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 25565.816419 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81723.279965 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 65080.001655 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 86397.192029 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 74476.815508 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 14579.571463 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81723.279965 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 65080.001655 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 86397.192029 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 74476.815508 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 14579.571463 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.writebacks::writebacks 75044 # number of writebacks
system.l2c.writebacks::total 75044 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst 2311 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 17559 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 4416 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 18739 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 43025 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 13 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 18684 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 20878 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 39562 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2311 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 36243 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 4416 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 39617 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 82587 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2311 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 36243 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 4416 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 39617 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 82587 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 159781752 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 924365000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 326545000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 983466501 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2394158253 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 281010 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 281010 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 988054509 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1484814274 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2472868783 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 159781752 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1912419509 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 326545000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2468280775 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 4867027036 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 159781752 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1912419509 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 326545000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2468280775 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 4867027036 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277028500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292401500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 569430000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 343013500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402731500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 745745000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 620042000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 695133000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1315175000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018289 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172934 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014852 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.072637 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.021077 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.764706 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.448276 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.414077 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.236043 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.130726 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018289 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.247126 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014852 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.114358 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.035234 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018289 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.247126 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014852 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.114358 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.035234 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69139.659022 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 52643.373768 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73945.878623 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 52482.336357 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 55645.746729 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21616.153846 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21616.153846 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52882.386480 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71118.606859 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62506.162049 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69139.659022 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52766.589659 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73945.878623 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69139.659022 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52766.589659 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73945.878623 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62303.576116 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58932.120503 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41685 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.tagsinuse 1.254871 # Cycle average of tags in use
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.warmup_cycle 1694871315000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.254871 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.078429 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.078429 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_miss_latency::tsunami.ide 9512963 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9512963 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 4344125507 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 4344125507 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 4353638470 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4353638470 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 4353638470 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4353638470 # number of overall miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54988.225434 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 54988.225434 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104546.724755 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 104546.724755 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 104341.245536 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 104341.245536 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 104341.245536 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 113861 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.blocked::no_mshrs 11412 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.977305 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 17349 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5924213 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5924213 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3445287507 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 3445287507 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 3451211720 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3451211720 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 3451211720 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3451211720 # number of overall MSHR miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85858.159420 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 85858.159420 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199380.064062 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 199380.064062 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.read_hits 4916475 # DTB read hits
system.cpu0.dtb.read_misses 6063 # DTB read misses
system.cpu0.dtb.read_acv 126 # DTB read access violations
system.cpu0.dtb.read_accesses 427415 # DTB read accesses
system.cpu0.dtb.write_hits 3510632 # DTB write hits
system.cpu0.dtb.write_misses 668 # DTB write misses
system.cpu0.dtb.write_acv 84 # DTB write access violations
system.cpu0.dtb.write_accesses 162993 # DTB write accesses
system.cpu0.dtb.data_hits 8427107 # DTB hits
system.cpu0.dtb.data_misses 6731 # DTB misses
system.cpu0.dtb.data_acv 210 # DTB access violations
system.cpu0.dtb.data_accesses 590408 # DTB accesses
system.cpu0.itb.fetch_hits 2754785 # ITB hits
system.cpu0.itb.fetch_misses 3015 # ITB misses
system.cpu0.itb.fetch_acv 104 # ITB acv
system.cpu0.itb.fetch_accesses 2757800 # ITB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.numCycles 928378822 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.committedInsts 33851772 # Number of instructions committed
system.cpu0.committedOps 33851772 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 31712153 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 169925 # Number of float alu accesses
system.cpu0.num_func_calls 812668 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4695347 # number of instructions that are conditional controls
system.cpu0.num_int_insts 31712153 # number of integer instructions
system.cpu0.num_fp_insts 169925 # number of float instructions
system.cpu0.num_int_register_reads 44553309 # number of times the integer registers were read
system.cpu0.num_int_register_writes 23136473 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 87700 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 89305 # number of times the floating registers were written
system.cpu0.num_mem_refs 8457205 # number of memory refs
system.cpu0.num_load_insts 4937806 # Number of load instructions
system.cpu0.num_store_insts 3519399 # Number of store instructions
system.cpu0.num_idle_cycles 213007832176.448029 # Number of idle cycles
system.cpu0.num_busy_cycles -212079453354.448029 # Number of busy cycles
system.cpu0.not_idle_fraction -228.440641 # Percentage of non-idle cycles
system.cpu0.idle_fraction 229.440641 # Percentage of idle cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1819523663000 98.74% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 39251000 0.00% 98.74% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 365640000 0.02% 98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22768477500 1.24% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1842697031500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.callpal::total 192238 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.kern.mode_good::kernel 1907
system.cpu0.kern.mode_good::user 1738
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.mode_good::idle 169
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.mode_switch_good::kernel 0.321965 # fraction of useful protection mode switches
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 29806042000 1.62% 1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2607375500 0.14% 1.76% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1810283609500 98.24% 100.00% # number of ticks spent at the given mode
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.throughput 110454960 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 786209 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 786164 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 371427 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 150852 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 133572 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 847417 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1371009 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 2218426 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 27116864 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 55346243 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 82463107 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 203524040 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2135036000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1907460021 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2223763109 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.iobus.throughput 1469142 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 2977 # Transaction distribution
system.iobus.trans_dist::ReadResp 2977 # Transaction distribution
system.iobus.trans_dist::WriteReq 21029 # Transaction distribution
system.iobus.trans_dist::WriteResp 21029 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 13314 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 34698 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.uart.pio 8346 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ide.pio 2386 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 34698 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 48012 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 15747 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107368 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.uart.pio 4173 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ide.pio 1554 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 1107368 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 1123115 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2707184 # Total data (bytes)
system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6219000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 1797000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 157278470 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 9565000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17530000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.replacements 950939 # number of replacements
system.cpu0.icache.tagsinuse 511.192426 # Cycle average of tags in use
system.cpu0.icache.total_refs 43369559 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 951450 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 45.582594 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 10375508000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 249.451681 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 99.242283 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst 162.498462 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.487210 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.193833 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst 0.317380 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998423 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 33330806 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7798498 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2240255 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 43369559 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 33330806 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7798498 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2240255 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 43369559 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 33330806 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7798498 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2240255 # number of overall hits
system.cpu0.icache.overall_hits::total 43369559 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 527907 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 126362 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 313908 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 968177 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 527907 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 126362 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 313908 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 968177 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 527907 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 126362 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 313908 # number of overall misses
system.cpu0.icache.overall_misses::total 968177 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1815628000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4475089488 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6290717488 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1815628000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4475089488 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6290717488 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1815628000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4475089488 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6290717488 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 33858713 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7924860 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2554163 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 44337736 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 33858713 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7924860 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2554163 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 44337736 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 33858713 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7924860 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2554163 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 44337736 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015591 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015945 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122901 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.021836 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015591 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015945 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122901 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.021836 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015591 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015945 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122901 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.021836 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14368.465203 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14256.054283 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6497.487017 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14368.465203 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14256.054283 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6497.487017 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14368.465203 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14256.054283 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6497.487017 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 6305 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1097 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 216 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.189815 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 1097 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16554 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 16554 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16554 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 16554 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16554 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 16554 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126362 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297354 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 423716 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 126362 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 297354 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 423716 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 126362 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 297354 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 423716 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1562904000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3675281468 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5238185468 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1562904000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3675281468 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5238185468 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1562904000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3675281468 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5238185468 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015945 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116419 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009557 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015945 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116419 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009557 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015945 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116419 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009557 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12368.465203 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12359.953012 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12362.491546 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12368.465203 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12359.953012 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12362.491546 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12368.465203 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12359.953012 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12362.491546 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.replacements 1391818 # number of replacements
system.cpu0.dcache.tagsinuse 511.997813 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13288463 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1392330 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 9.544047 # Average number of references to valid blocks.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.occ_blocks::cpu0.data 250.572227 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 130.318836 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data 131.106750 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.489399 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.254529 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data 0.256068 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 4079887 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1087384 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 2393640 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7560911 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3214191 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 837673 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 1292223 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5344087 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117280 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19306 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47521 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184107 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126439 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21329 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51518 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 199286 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7294078 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 1925057 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 3685863 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12904998 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7294078 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 1925057 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 3685863 # number of overall hits
system.cpu0.dcache.overall_hits::total 12904998 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 720489 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 99382 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 533191 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1353062 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 169071 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 45123 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 589200 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 803394 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9725 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2154 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6827 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 18706 # number of LoadLockedReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_misses::cpu0.data 889560 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 144505 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1122391 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2156456 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 889560 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 144505 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1122391 # number of overall misses
system.cpu0.dcache.overall_misses::total 2156456 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2259316500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9366343500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11625660000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1618937000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17797464172 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 19416401172 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28461500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102597000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 131058500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 25000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 25000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 3878253500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 27163807672 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 31042061172 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 3878253500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 27163807672 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 31042061172 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4800376 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1186766 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 2926831 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8913973 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383262 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 882796 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 1881423 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6147481 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127005 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21460 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54348 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 202813 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126439 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21329 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51519 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199287 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8183638 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2069562 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 4808254 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15061454 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8183638 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2069562 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 4808254 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15061454 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150090 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083742 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182173 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.151791 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049973 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051114 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.313167 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.130687 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076572 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100373 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.125616 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092233 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108700 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069824 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233430 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.143177 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108700 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069824 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233430 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.143177 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22733.659013 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17566.582144 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 8592.111817 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35878.310396 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30206.151005 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24167.968857 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13213.324048 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15028.123627 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7006.227948 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 25000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26838.195910 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24201.733328 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14394.942986 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26838.195910 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24201.733328 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14394.942986 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 565985 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1720 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 17882 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 31.651102 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 245.714286 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.writebacks::writebacks 835411 # number of writebacks
system.cpu0.dcache.writebacks::total 835411 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280380 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 280380 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 500979 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 500979 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1414 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1414 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 781359 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 781359 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 781359 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 781359 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 99382 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252811 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 352193 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 45123 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88221 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 133344 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2154 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5413 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7567 # number of LoadLockedReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_mshr_misses::cpu1.data 144505 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 341032 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 485537 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 144505 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 341032 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 485537 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2060552500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4252408235 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6312960735 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1528691000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2589747290 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4118438290 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24153500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66206002 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90359502 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 23000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 23000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3589243500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6842155525 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10431399025 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3589243500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6842155525 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10431399025 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295697000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311546500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607243500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 363354500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427379500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790734000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 659051500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 738926000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397977500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083742 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086377 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039510 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051114 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046891 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021691 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100373 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099599 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037310 # mshr miss rate for LoadLockedReq accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032237 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032237 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20733.659013 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16820.503202 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17924.719500 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33878.310396 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29355.224833 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30885.816310 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11213.324048 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12230.925919 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11941.258359 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 23000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.read_hits 1206143 # DTB read hits
system.cpu1.dtb.read_misses 1395 # DTB read misses
system.cpu1.dtb.read_acv 35 # DTB read access violations
system.cpu1.dtb.read_accesses 142828 # DTB read accesses
system.cpu1.dtb.write_hits 904590 # DTB write hits
system.cpu1.dtb.write_misses 190 # DTB write misses
system.cpu1.dtb.write_acv 23 # DTB write access violations
system.cpu1.dtb.write_accesses 58592 # DTB write accesses
system.cpu1.dtb.data_hits 2110733 # DTB hits
system.cpu1.dtb.data_misses 1585 # DTB misses
system.cpu1.dtb.data_acv 58 # DTB access violations
system.cpu1.dtb.data_accesses 201420 # DTB accesses
system.cpu1.itb.fetch_hits 862559 # ITB hits
system.cpu1.itb.fetch_misses 707 # ITB misses
system.cpu1.itb.fetch_acv 34 # ITB acv
system.cpu1.itb.fetch_accesses 863266 # ITB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.numCycles 953614983 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.committedInsts 7923216 # Number of instructions committed
system.cpu1.committedOps 7923216 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 7378774 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 44696 # Number of float alu accesses
system.cpu1.num_func_calls 212761 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1003934 # number of instructions that are conditional controls
system.cpu1.num_int_insts 7378774 # number of integer instructions
system.cpu1.num_fp_insts 44696 # number of float instructions
system.cpu1.num_int_register_reads 10322317 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5366754 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24140 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 24473 # number of times the floating registers were written
system.cpu1.num_mem_refs 2118035 # number of memory refs
system.cpu1.num_load_insts 1211092 # Number of load instructions
system.cpu1.num_store_insts 906943 # Number of store instructions
system.cpu1.num_idle_cycles -710985323.015638 # Number of idle cycles
system.cpu1.num_busy_cycles 1664600306.015638 # Number of busy cycles
system.cpu1.not_idle_fraction 1.745569 # Percentage of non-idle cycles
system.cpu1.idle_fraction -0.745569 # Percentage of idle cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.branchPred.lookups 8997247 # Number of BP lookups
system.cpu2.branchPred.condPredicted 8318296 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 124435 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 7453298 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 6389224 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.branchPred.BTBHitPct 85.723448 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 282371 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 13443 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dtb.read_hits 3184667 # DTB read hits
system.cpu2.dtb.read_misses 11563 # DTB read misses
system.cpu2.dtb.read_acv 122 # DTB read access violations
system.cpu2.dtb.read_accesses 218108 # DTB read accesses
system.cpu2.dtb.write_hits 2003168 # DTB write hits
system.cpu2.dtb.write_misses 2582 # DTB write misses
system.cpu2.dtb.write_acv 105 # DTB write access violations
system.cpu2.dtb.write_accesses 82984 # DTB write accesses
system.cpu2.dtb.data_hits 5187835 # DTB hits
system.cpu2.dtb.data_misses 14145 # DTB misses
system.cpu2.dtb.data_acv 227 # DTB access violations
system.cpu2.dtb.data_accesses 301092 # DTB accesses
system.cpu2.itb.fetch_hits 370432 # ITB hits
system.cpu2.itb.fetch_misses 5697 # ITB misses
system.cpu2.itb.fetch_acv 245 # ITB acv
system.cpu2.itb.fetch_accesses 376129 # ITB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.numCycles 31194709 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.fetch.icacheStallCycles 8336463 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 36595534 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 8997247 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 6671595 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 8714180 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 607609 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 9678498 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 11323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1980 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 64467 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 86613 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2554168 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 86055 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 27288913 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.341040 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.295561 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.fetch.rateDist::0 18574733 68.07% 68.07% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 269160 0.99% 69.05% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 428961 1.57% 70.63% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 4866915 17.83% 88.46% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 754326 2.76% 91.22% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 165422 0.61% 91.83% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 191254 0.70% 92.53% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 429367 1.57% 94.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1608775 5.90% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.fetch.rateDist::total 27288913 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.288422 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.173133 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 8484758 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 9763089 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 8105885 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 306526 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 382761 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 165822 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 12764 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36197990 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 39851 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 382761 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 8844170 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 2798398 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 5770090 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 7975185 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1272419 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 35047656 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 232046 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 447152 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 23489226 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 43822690 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 43659490 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 163200 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 21694214 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1795012 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 501276 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 59320 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3724979 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3343402 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2093050 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 368261 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 257932 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 32557394 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 620599 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 32107794 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 34091 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2143269 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1080696 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 438167 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 27288913 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.176588 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.573888 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.issued_per_cycle::0 15150790 55.52% 55.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3070151 11.25% 66.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1548988 5.68% 72.45% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 5689584 20.85% 93.30% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 903005 3.31% 96.61% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 480338 1.76% 98.37% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 283929 1.04% 99.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 143393 0.53% 99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 18735 0.07% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.issued_per_cycle::total 27288913 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.fu_full::IntAlu 33803 13.75% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.75% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 111727 45.45% 59.20% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 100297 40.80% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::IntAlu 26449669 82.38% 82.39% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 20147 0.06% 82.45% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.45% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 8446 0.03% 82.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.47% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.48% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3312033 10.32% 92.79% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2025467 6.31% 99.10% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 288360 0.90% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::total 32107794 # Type of FU issued
system.cpu2.iq.rate 1.029271 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 245827 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 91550157 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 35210267 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 31710626 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 234262 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 114809 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 110859 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 32229265 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 121908 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 186278 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.lsq.thread0.squashedLoads 409987 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1098 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 3916 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 156672 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 4171 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 28368 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.iewSquashCycles 382761 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 2017515 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 205037 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 34446466 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 224960 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3343402 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2093050 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 551127 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 142834 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 3916 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 63764 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 127616 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 191380 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 31948816 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3204490 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 158978 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.exec_nop 1268473 # number of nop insts executed
system.cpu2.iew.exec_refs 5214665 # number of memory reference insts executed
system.cpu2.iew.exec_branches 7427208 # Number of branches executed
system.cpu2.iew.exec_stores 2010175 # Number of stores executed
system.cpu2.iew.exec_rate 1.024174 # Inst execution rate
system.cpu2.iew.wb_sent 31853816 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 31821485 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 18500784 # num instructions producing a value
system.cpu2.iew.wb_consumers 21694431 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.wb_rate 1.020092 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.852790 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.commitSquashedInsts 2318994 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 182432 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 176935 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 26906152 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.192355 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.846387 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.committed_per_cycle::0 16157542 60.05% 60.05% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2331595 8.67% 68.72% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1218913 4.53% 73.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 5433463 20.19% 93.44% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 503772 1.87% 95.31% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 185469 0.69% 96.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 177448 0.66% 96.66% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 178843 0.66% 97.33% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 719107 2.67% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.committed_per_cycle::total 26906152 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 32081688 # Number of instructions committed
system.cpu2.commit.committedOps 32081688 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.refs 4869793 # Number of memory references committed
system.cpu2.commit.loads 2933415 # Number of loads committed
system.cpu2.commit.membars 63859 # Number of memory barriers committed
system.cpu2.commit.branches 7280639 # Number of branches committed
system.cpu2.commit.fp_insts 109636 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 30638732 # Number of committed integer instructions.
system.cpu2.commit.function_calls 228563 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 719107 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.rob.rob_reads 60513787 # The number of ROB reads
system.cpu2.rob.rob_writes 69183653 # The number of ROB writes
system.cpu2.timesIdled 245794 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 3905796 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1746583104 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 30918811 # Number of Instructions Simulated
system.cpu2.committedOps 30918811 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 30918811 # Number of Instructions Simulated
system.cpu2.cpi 1.008923 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.008923 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.991156 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.991156 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 42017360 # number of integer regfile reads
system.cpu2.int_regfile_writes 22376128 # number of integer regfile writes
system.cpu2.fp_regfile_reads 67819 # number of floating regfile reads
system.cpu2.fp_regfile_writes 67985 # number of floating regfile writes
system.cpu2.misc_regfile_reads 5215792 # number of misc regfile reads
system.cpu2.misc_regfile_writes 257331 # number of misc regfile writes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink