2006-04-06 06:51:46 +02:00
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/*
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2013-07-18 14:31:16 +02:00
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* Copyright (c) 2011,2013 ARM Limited
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2012-01-17 19:55:08 +01:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-04-06 06:51:46 +02:00
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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2012-01-17 19:55:08 +01:00
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* Andreas Hansson
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2006-04-06 06:51:46 +02:00
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*/
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/**
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2006-08-15 01:25:07 +02:00
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* @file
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* Port object definitions.
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2006-04-06 06:51:46 +02:00
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*/
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2013-09-04 19:22:57 +02:00
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#include "arch/vtophys.hh"
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2006-04-06 06:51:46 +02:00
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#include "base/chunk_generator.hh"
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2012-01-17 19:55:08 +01:00
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#include "cpu/base.hh"
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2007-02-19 01:57:46 +01:00
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#include "cpu/thread_context.hh"
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2012-01-17 19:55:08 +01:00
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#include "mem/fs_translating_port_proxy.hh"
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2013-07-18 14:31:16 +02:00
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#include "sim/system.hh"
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2012-01-17 19:55:08 +01:00
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using namespace TheISA;
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FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc)
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2013-07-18 14:31:16 +02:00
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: PortProxy(tc->getCpuPtr()->getDataPort(),
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tc->getSystemPtr()->cacheLineSize()), _tc(tc)
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2012-01-17 19:55:08 +01:00
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{
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}
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2013-07-18 14:31:16 +02:00
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FSTranslatingPortProxy::FSTranslatingPortProxy(MasterPort &port,
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unsigned int cacheLineSize)
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: PortProxy(port, cacheLineSize), _tc(NULL)
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2012-01-17 19:55:08 +01:00
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{
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}
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FSTranslatingPortProxy::~FSTranslatingPortProxy()
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{
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}
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2006-04-06 06:51:46 +02:00
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void
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2012-02-29 10:47:51 +01:00
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FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) const
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2006-04-06 06:51:46 +02:00
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{
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Addr paddr;
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for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
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2012-01-17 19:55:08 +01:00
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gen.next())
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2006-04-06 06:51:46 +02:00
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{
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2012-01-17 19:55:08 +01:00
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if (_tc)
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paddr = TheISA::vtophys(_tc,gen.addr());
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2006-04-06 06:51:46 +02:00
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else
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paddr = TheISA::vtophys(gen.addr());
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2012-01-17 19:55:08 +01:00
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PortProxy::readBlob(paddr, p, gen.size());
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2006-04-06 06:51:46 +02:00
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p += gen.size();
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}
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}
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void
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2012-02-29 10:47:51 +01:00
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FSTranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size) const
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2006-04-06 06:51:46 +02:00
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{
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Addr paddr;
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for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
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2012-01-17 19:55:08 +01:00
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gen.next())
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2006-04-06 06:51:46 +02:00
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{
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2012-01-17 19:55:08 +01:00
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if (_tc)
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paddr = TheISA::vtophys(_tc,gen.addr());
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2006-04-06 06:51:46 +02:00
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else
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paddr = TheISA::vtophys(gen.addr());
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2012-01-17 19:55:08 +01:00
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PortProxy::writeBlob(paddr, p, gen.size());
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2006-04-06 06:51:46 +02:00
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p += gen.size();
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}
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}
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2012-01-17 19:55:08 +01:00
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void
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2012-02-29 10:47:51 +01:00
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FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) const
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2012-01-17 19:55:08 +01:00
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{
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Addr paddr;
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for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done();
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gen.next())
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{
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if (_tc)
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paddr = TheISA::vtophys(_tc,gen.addr());
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else
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paddr = TheISA::vtophys(gen.addr());
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PortProxy::memsetBlob(paddr, v, gen.size());
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}
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}
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2007-02-19 01:57:46 +01:00
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void
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CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
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{
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uint8_t *dst = (uint8_t *)dest;
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2012-02-24 17:45:30 +01:00
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tc->getVirtProxy().readBlob(src, dst, cplen);
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2007-02-19 01:57:46 +01:00
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}
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void
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CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
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{
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uint8_t *src = (uint8_t *)source;
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2012-02-24 17:45:30 +01:00
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tc->getVirtProxy().writeBlob(dest, src, cplen);
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2007-02-19 01:57:46 +01:00
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}
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void
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CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
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{
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char *start = dst;
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2012-02-24 17:45:30 +01:00
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FSTranslatingPortProxy &vp = tc->getVirtProxy();
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2007-02-19 01:57:46 +01:00
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2012-01-12 22:27:20 +01:00
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bool foundNull = false;
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while ((dst - start + 1) < maxlen && !foundNull) {
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2012-02-24 17:45:30 +01:00
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vp.readBlob(vaddr++, (uint8_t*)dst, 1);
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2012-05-11 01:04:27 +02:00
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if (*dst == '\0')
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2012-01-12 22:27:20 +01:00
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foundNull = true;
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dst++;
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}
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2007-02-19 01:57:46 +01:00
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2012-01-12 22:27:20 +01:00
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if (!foundNull)
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*dst = '\0';
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2007-02-19 01:57:46 +01:00
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}
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void
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CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
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{
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2012-02-24 17:45:30 +01:00
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FSTranslatingPortProxy &vp = tc->getVirtProxy();
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2007-02-19 01:57:46 +01:00
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for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();
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2012-02-24 17:45:30 +01:00
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gen.next())
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2007-02-19 01:57:46 +01:00
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{
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2012-02-24 17:45:30 +01:00
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vp.writeBlob(gen.addr(), (uint8_t*)src, gen.size());
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2007-02-19 01:57:46 +01:00
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src += gen.size();
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}
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}
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