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gem5/src/mem
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Andreas Hansson 9779ba2e37 mem: Add const getters for write packet data 
This patch takes a first step in tightening up how we use the data
pointer in write packets. A const getter is added for the pointer
itself (getConstPtr), and a number of member functions are also made
const accordingly. In a range of places throughout the memory system
the new member is used.

The patch also removes the unused isReadWrite function.
2014-12-02 06:07:36 -05:00
..
cache mem: Add const getters for write packet data 2014-12-02 06:07:36 -05:00
protocol ruby: interface with classic memory controller 2014-11-06 05:42:21 -06:00
ruby mem: Add const getters for write packet data 2014-12-02 06:07:36 -05:00
slicc ruby: interface with classic memory controller 2014-11-06 05:42:21 -06:00
abstract_mem.cc mem: Add const getters for write packet data 2014-12-02 06:07:36 -05:00
abstract_mem.hh mem: Dynamically determine page bytes in memory components 2014-10-16 05:49:43 -04:00
AbstractMemory.py mem: Change AbstractMemory defaults to match the common case 2013-08-19 03:52:33 -04:00
addr_mapper.cc mem: Set the cache line size on a system level 2013-07-18 08:31:16 -04:00
addr_mapper.hh mem: Set the cache line size on a system level 2013-07-18 08:31:16 -04:00
AddrMapper.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
bridge.cc mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
bridge.hh mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
Bridge.py mem: Tidy up the bridge with const and additional checks 2013-06-27 05:49:49 -04:00
coherent_xbar.cc mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
coherent_xbar.hh mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
comm_monitor.cc misc: Fix a bunch of minor issues identified by static analysis 2014-09-27 09:08:29 -04:00
comm_monitor.hh misc: Fix a bunch of minor issues identified by static analysis 2014-09-27 09:08:29 -04:00
CommMonitor.py mem: Auto-generate CommMonitor trace file names 2014-05-09 18:58:46 -04:00
dram_ctrl.cc mem: Add a GDDR5 DRAM config 2014-12-02 06:07:32 -05:00
dram_ctrl.hh mem: Add DRAM device size and check against config 2014-10-20 18:03:52 -04:00
DRAMCtrl.py mem: Add a GDDR5 DRAM config 2014-12-02 06:07:32 -05:00
drampower.cc mem: Add a GDDR5 DRAM config 2014-12-02 06:07:32 -05:00
drampower.hh mem: Add DRAMPower wrapping class 2014-07-29 17:29:36 +01:00
dramsim2.cc mem: Dynamically determine page bytes in memory components 2014-10-16 05:49:43 -04:00
dramsim2.hh mem: Fix DRAMSim2 cycle check when restoring from checkpoint 2014-08-26 10:14:38 -04:00
DRAMSim2.py mem: Add a wrapped DRAMSim2 memory controller 2014-02-18 05:50:53 -05:00
dramsim2_wrapper.cc mem: Add a wrapped DRAMSim2 memory controller 2014-02-18 05:50:53 -05:00
dramsim2_wrapper.hh mem: Add a wrapped DRAMSim2 memory controller 2014-02-18 05:50:53 -05:00
external_master.cc mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
external_master.hh mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
external_slave.cc mem: Add const getters for write packet data 2014-12-02 06:07:36 -05:00
external_slave.hh mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
ExternalMaster.py mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
ExternalSlave.py mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
fs_translating_port_proxy.cc arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00
fs_translating_port_proxy.hh arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00
mem_object.cc Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
mem_object.hh Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
MemObject.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
multi_level_page_table.cc mem: adding a multi-level page table class 2014-04-01 12:18:12 -05:00
multi_level_page_table.hh mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
multi_level_page_table_impl.hh mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
noncoherent_xbar.cc mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
noncoherent_xbar.hh mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
packet.cc mem: Add const getters for write packet data 2014-12-02 06:07:36 -05:00
packet.hh mem: Add const getters for write packet data 2014-12-02 06:07:36 -05:00
packet_access.hh mem: Add const getters for write packet data 2014-12-02 06:07:36 -05:00
packet_queue.cc mem: Allow packet queue to move next send event forward 2014-10-09 17:51:52 -04:00
packet_queue.hh mem: Packet queue clean up 2014-09-03 07:42:28 -04:00
page_table.cc mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
page_table.hh mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
physical.cc mem: Modernise PhysicalMemory with C++11 features 2014-10-16 05:50:01 -04:00
physical.hh mem: Modernise PhysicalMemory with C++11 features 2014-10-16 05:50:01 -04:00
port.cc mem: Set the cache line size on a system level 2013-07-18 08:31:16 -04:00
port.hh misc: Move AddrRangeList from port.hh to addr_range.hh 2014-10-16 05:49:59 -04:00
port_proxy.cc mem: Set the cache line size on a system level 2013-07-18 08:31:16 -04:00
port_proxy.hh arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00
qport.hh ruby: Simplify RubyPort flow control and routing 2014-02-23 19:16:16 -06:00
request.hh mem: Add accessor function for vaddr 2014-09-09 04:36:33 -04:00
SConscript mem: Add ExternalMaster and ExternalSlave ports 2014-10-16 05:49:56 -04:00
se_translating_port_proxy.cc arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
se_translating_port_proxy.hh mem: adding a multi-level page table class 2014-04-01 12:18:12 -05:00
simple_mem.cc arm, mem: Fix drain bug and provide drain prints for more components. 2014-10-29 23:18:26 -05:00
simple_mem.hh mem: Add an internal packet queue in SimpleMemory 2013-08-19 03:52:25 -04:00
SimpleMemory.py mem: Add an internal packet queue in SimpleMemory 2013-08-19 03:52:25 -04:00
snoop_filter.cc mem: Add access statistics for the snoop filter 2014-04-25 12:36:16 +01:00
snoop_filter.hh mem: Add access statistics for the snoop filter 2014-04-25 12:36:16 +01:00
tport.cc mem: Replace check with panic where inhibited should not happen 2013-04-22 13:20:33 -04:00
tport.hh Port: Hide the queue implementation in SimpleTimingPort 2012-07-09 12:35:42 -04:00
xbar.cc mem: Output precise range when XBar has conflicts 2014-09-27 09:08:32 -04:00
xbar.hh mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00
XBar.py mem: Rename Bus to XBar to better reflect its behaviour 2014-09-20 17:18:32 -04:00