edc77fc03c
The new location seems like a better fit. The iterator typedefs are removed in favour of using C++11 auto.
455 lines
13 KiB
C++
455 lines
13 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Andreas Hansson
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* William Wang
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*/
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/**
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* @file
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* Port Object Declaration.
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*/
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#ifndef __MEM_PORT_HH__
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#define __MEM_PORT_HH__
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#include "base/addr_range.hh"
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#include "mem/packet.hh"
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class MemObject;
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/**
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* Ports are used to interface memory objects to each other. A port is
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* either a master or a slave and the connected peer is always of the
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* opposite role. Each port has a name, an owner, and an identifier.
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*/
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class Port
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{
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private:
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/** Descriptive name (for DPRINTF output) */
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std::string portName;
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protected:
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/**
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* A numeric identifier to distinguish ports in a vector, and set
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* to InvalidPortID in case this port is not part of a vector.
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*/
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const PortID id;
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/** A reference to the MemObject that owns this port. */
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MemObject& owner;
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/**
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* Abstract base class for ports
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*
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* @param _name Port name including the owners name
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* @param _owner The MemObject that is the structural owner of this port
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* @param _id A port identifier for vector ports
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*/
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Port(const std::string& _name, MemObject& _owner, PortID _id);
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/**
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* Virtual destructor due to inheritance.
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*/
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virtual ~Port();
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public:
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/** Return port name (for DPRINTF). */
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const std::string name() const { return portName; }
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/** Get the port id. */
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PortID getId() const { return id; }
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};
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/** Forward declaration */
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class BaseSlavePort;
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/**
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* A BaseMasterPort is a protocol-agnostic master port, responsible
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* only for the structural connection to a slave port. The final
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* master port that inherits from the base class must override the
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* bind member function for the specific slave port class.
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*/
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class BaseMasterPort : public Port
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{
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protected:
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BaseSlavePort* _baseSlavePort;
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BaseMasterPort(const std::string& name, MemObject* owner,
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PortID id = InvalidPortID);
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virtual ~BaseMasterPort();
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public:
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virtual void bind(BaseSlavePort& slave_port) = 0;
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virtual void unbind() = 0;
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BaseSlavePort& getSlavePort() const;
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bool isConnected() const;
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};
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/**
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* A BaseSlavePort is a protocol-agnostic slave port, responsible
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* only for the structural connection to a master port.
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*/
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class BaseSlavePort : public Port
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{
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protected:
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BaseMasterPort* _baseMasterPort;
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BaseSlavePort(const std::string& name, MemObject* owner,
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PortID id = InvalidPortID);
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virtual ~BaseSlavePort();
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public:
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BaseMasterPort& getMasterPort() const;
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bool isConnected() const;
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};
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/** Forward declaration */
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class SlavePort;
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/**
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* A MasterPort is a specialisation of a BaseMasterPort, which
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* implements the default protocol for the three different level of
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* transport functions. In addition to the basic functionality of
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* sending packets, it also has functions to receive range changes or
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* determine if the port is snooping or not.
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*/
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class MasterPort : public BaseMasterPort
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{
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friend class SlavePort;
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private:
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SlavePort* _slavePort;
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public:
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MasterPort(const std::string& name, MemObject* owner,
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PortID id = InvalidPortID);
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virtual ~MasterPort();
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/**
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* Bind this master port to a slave port. This also does the
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* mirror action and binds the slave port to the master port.
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*/
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void bind(BaseSlavePort& slave_port);
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/**
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* Unbind this master port and the associated slave port.
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*/
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void unbind();
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/**
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* Send an atomic request packet, where the data is moved and the
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* state is updated in zero time, without interleaving with other
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* memory accesses.
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*
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* @param pkt Packet to send.
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*
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* @return Estimated latency of access.
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*/
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Tick sendAtomic(PacketPtr pkt);
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/**
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* Send a functional request packet, where the data is instantly
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* updated everywhere in the memory system, without affecting the
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* current state of any block or moving the block.
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*
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* @param pkt Packet to send.
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*/
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void sendFunctional(PacketPtr pkt);
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/**
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* Attempt to send a timing request to the slave port by calling
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* its corresponding receive function. If the send does not
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* succeed, as indicated by the return value, then the sender must
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* wait for a recvRetry at which point it can re-issue a
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* sendTimingReq.
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*
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* @param pkt Packet to send.
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*
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* @return If the send was succesful or not.
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*/
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bool sendTimingReq(PacketPtr pkt);
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/**
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* Attempt to send a timing snoop response packet to the slave
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* port by calling its corresponding receive function. If the send
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* does not succeed, as indicated by the return value, then the
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* sender must wait for a recvRetry at which point it can re-issue
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* a sendTimingSnoopResp.
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*
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* @param pkt Packet to send.
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*/
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bool sendTimingSnoopResp(PacketPtr pkt);
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/**
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* Send a retry to the slave port that previously attempted a
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* sendTimingResp to this master port and failed.
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*/
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virtual void sendRetry();
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/**
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* Determine if this master port is snooping or not. The default
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* implementation returns false and thus tells the neighbour we
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* are not snooping. Any master port that wants to receive snoop
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* requests (e.g. a cache connected to a bus) has to override this
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* function.
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*
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* @return true if the port should be considered a snooper
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*/
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virtual bool isSnooping() const { return false; }
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/**
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* Get the address ranges of the connected slave port.
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*/
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AddrRangeList getAddrRanges() const;
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/** Inject a PrintReq for the given address to print the state of
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* that address throughout the memory system. For debugging.
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*/
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void printAddr(Addr a);
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protected:
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/**
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* Receive an atomic snoop request packet from the slave port.
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*/
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virtual Tick recvAtomicSnoop(PacketPtr pkt)
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{
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panic("%s was not expecting an atomic snoop request\n", name());
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return 0;
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}
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/**
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* Receive a functional snoop request packet from the slave port.
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*/
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virtual void recvFunctionalSnoop(PacketPtr pkt)
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{
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panic("%s was not expecting a functional snoop request\n", name());
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}
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/**
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* Receive a timing response from the slave port.
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*/
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virtual bool recvTimingResp(PacketPtr pkt) = 0;
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/**
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* Receive a timing snoop request from the slave port.
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*/
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virtual void recvTimingSnoopReq(PacketPtr pkt)
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{
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panic("%s was not expecting a timing snoop request\n", name());
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}
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/**
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* Called by the slave port if sendTimingReq or
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* sendTimingSnoopResp was called on this master port (causing
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* recvTimingReq and recvTimingSnoopResp to be called on the
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* slave port) and was unsuccesful.
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*/
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virtual void recvRetry() = 0;
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/**
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* Called to receive an address range change from the peer slave
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* port. The default implementation ignores the change and does
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* nothing. Override this function in a derived class if the owner
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* needs to be aware of the address ranges, e.g. in an
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* interconnect component like a bus.
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*/
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virtual void recvRangeChange() { }
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};
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/**
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* A SlavePort is a specialisation of a port. In addition to the
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* basic functionality of sending packets to its master peer, it also
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* has functions specific to a slave, e.g. to send range changes
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* and get the address ranges that the port responds to.
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*/
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class SlavePort : public BaseSlavePort
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{
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friend class MasterPort;
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private:
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MasterPort* _masterPort;
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public:
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SlavePort(const std::string& name, MemObject* owner,
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PortID id = InvalidPortID);
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virtual ~SlavePort();
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/**
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* Send an atomic snoop request packet, where the data is moved
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* and the state is updated in zero time, without interleaving
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* with other memory accesses.
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*
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* @param pkt Snoop packet to send.
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*
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* @return Estimated latency of access.
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*/
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Tick sendAtomicSnoop(PacketPtr pkt);
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/**
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* Send a functional snoop request packet, where the data is
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* instantly updated everywhere in the memory system, without
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* affecting the current state of any block or moving the block.
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*
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* @param pkt Snoop packet to send.
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*/
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void sendFunctionalSnoop(PacketPtr pkt);
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/**
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* Attempt to send a timing response to the master port by calling
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* its corresponding receive function. If the send does not
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* succeed, as indicated by the return value, then the sender must
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* wait for a recvRetry at which point it can re-issue a
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* sendTimingResp.
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*
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* @param pkt Packet to send.
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*
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* @return If the send was succesful or not.
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*/
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bool sendTimingResp(PacketPtr pkt);
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/**
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* Attempt to send a timing snoop request packet to the master port
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* by calling its corresponding receive function. Snoop requests
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* always succeed and hence no return value is needed.
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*
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* @param pkt Packet to send.
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*/
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void sendTimingSnoopReq(PacketPtr pkt);
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/**
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* Send a retry to the master port that previously attempted a
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* sendTimingReq or sendTimingSnoopResp to this slave port and
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* failed.
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*/
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void sendRetry();
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/**
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* Find out if the peer master port is snooping or not.
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*
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* @return true if the peer master port is snooping
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*/
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bool isSnooping() const { return _masterPort->isSnooping(); }
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/**
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* Called by the owner to send a range change
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*/
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void sendRangeChange() const {
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if (!_masterPort)
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fatal("%s cannot sendRangeChange() without master port", name());
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_masterPort->recvRangeChange();
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}
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/**
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* Get a list of the non-overlapping address ranges the owner is
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* responsible for. All slave ports must override this function
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* and return a populated list with at least one item.
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*
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* @return a list of ranges responded to
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*/
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virtual AddrRangeList getAddrRanges() const = 0;
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protected:
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/**
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* Called by the master port to unbind. Should never be called
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* directly.
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*/
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void unbind();
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/**
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* Called by the master port to bind. Should never be called
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* directly.
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*/
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void bind(MasterPort& master_port);
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/**
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* Receive an atomic request packet from the master port.
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*/
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virtual Tick recvAtomic(PacketPtr pkt) = 0;
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/**
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* Receive a functional request packet from the master port.
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*/
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virtual void recvFunctional(PacketPtr pkt) = 0;
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/**
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* Receive a timing request from the master port.
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*/
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virtual bool recvTimingReq(PacketPtr pkt) = 0;
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/**
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* Receive a timing snoop response from the master port.
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*/
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virtual bool recvTimingSnoopResp(PacketPtr pkt)
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{
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panic("%s was not expecting a timing snoop response\n", name());
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}
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/**
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* Called by the master port if sendTimingResp was called on this
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* slave port (causing recvTimingResp to be called on the master
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* port) and was unsuccesful.
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*/
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virtual void recvRetry() = 0;
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};
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#endif //__MEM_PORT_HH__
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