2016-05-31 17:55:47 +02:00
---------- Begin Simulation Statistics ----------
2016-10-14 00:21:40 +02:00
sim_seconds 0.058675 # Number of seconds simulated
sim_ticks 58675371500 # Number of ticks simulated
final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 111966 # Simulator instruction rate (inst/s)
host_op_rate 112523 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 72520515 # Simulator tick rate (ticks/s)
host_mem_usage 490592 # Number of bytes of host memory used
host_seconds 809.09 # Real time elapsed on the host
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sim_insts 90589799 # Number of instructions simulated
sim_ops 91041030 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory
system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory
system.physmem.bytes_written::total 6656 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory
system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory
system.physmem.num_writes::total 104 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 18533 # Number of read requests accepted
system.physmem.writeReqs 104 # Number of write requests accepted
system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue
system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 3245 # Per bank write bursts
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system.physmem.perBankRdBursts::1 921 # Per bank write bursts
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system.physmem.perBankRdBursts::2 952 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1031 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1065 # Per bank write bursts
system.physmem.perBankRdBursts::5 1118 # Per bank write bursts
system.physmem.perBankRdBursts::6 1097 # Per bank write bursts
system.physmem.perBankRdBursts::7 1096 # Per bank write bursts
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system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
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system.physmem.perBankRdBursts::9 962 # Per bank write bursts
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system.physmem.perBankRdBursts::10 932 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
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system.physmem.perBankRdBursts::12 904 # Per bank write bursts
system.physmem.perBankRdBursts::13 895 # Per bank write bursts
system.physmem.perBankRdBursts::14 1401 # Per bank write bursts
system.physmem.perBankRdBursts::15 903 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 3 # Per bank write bursts
system.physmem.perBankWrBursts::3 3 # Per bank write bursts
system.physmem.perBankWrBursts::4 12 # Per bank write bursts
system.physmem.perBankWrBursts::5 10 # Per bank write bursts
system.physmem.perBankWrBursts::6 15 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 1 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 1 # Per bank write bursts
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system.physmem.perBankWrBursts::11 3 # Per bank write bursts
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system.physmem.perBankWrBursts::12 5 # Per bank write bursts
system.physmem.perBankWrBursts::13 12 # Per bank write bursts
system.physmem.perBankWrBursts::14 7 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 58675363000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 18533 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 104 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see
2016-05-31 17:55:47 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see
2016-05-31 17:55:47 +02:00
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
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system.physmem.totQLat 819558662 # Total ticks spent queuing
system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers
system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.16 # Data bus utilization in percentage
system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-10-14 00:21:40 +02:00
system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing
system.physmem.readRowHits 15523 # Number of row buffer hits during reads
system.physmem.writeRowHits 12 # Number of row buffer hits during writes
system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes
system.physmem.avgGap 3148326.61 # Average gap between requests
system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ)
system.physmem_0.averagePower 336.815504 # Core power per rank (mW)
system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states
system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states
system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states
system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ)
system.physmem_1.averagePower 255.006594 # Core power per rank (mW)
system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states
system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states
system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 28234010 # Number of BP lookups
system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups
system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits
2016-05-31 17:55:47 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-10-14 00:21:40 +02:00
system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target.
2016-08-12 15:12:59 +02:00
system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions.
2016-10-14 00:21:40 +02:00
system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses.
2016-05-31 17:55:47 +02:00
system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 117350744 # number of cpu cycles simulated
2016-05-31 17:55:47 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-10-14 00:21:40 +02:00
system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed
system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total)
2016-05-31 17:55:47 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total)
2016-05-31 17:55:47 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups
2016-05-31 17:55:47 +02:00
system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
2016-10-14 00:21:40 +02:00
system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing
2016-05-31 17:55:47 +02:00
system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed
2016-10-14 00:21:40 +02:00
system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec)
2016-05-31 17:55:47 +02:00
system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ
2016-10-14 00:21:40 +02:00
system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph
2016-05-31 17:55:47 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed
2016-10-14 00:21:40 +02:00
system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-10-14 00:21:40 +02:00
system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available
2016-05-31 17:55:47 +02:00
system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
2016-10-14 00:21:40 +02:00
system.cpu.iq.fu_full::MemRead 9615894 47.83% 96.50% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 702925 3.50% 100.00% # attempts to use FU when none available
2016-05-31 17:55:47 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued
2016-05-31 17:55:47 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued
2016-05-31 17:55:47 +02:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::MemRead 24337772 24.01% 95.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5047242 4.98% 100.00% # Type of FU issued
2016-05-31 17:55:47 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued
system.cpu.iq.rate 0.863794 # Inst issue rate
system.cpu.iq.fu_busy_cnt 20102375 # FU busy when requested
2016-08-12 15:12:59 +02:00
system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst)
2016-10-14 00:21:40 +02:00
system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes
2016-08-12 15:12:59 +02:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
2016-10-14 00:21:40 +02:00
system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 238 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores
2016-05-31 17:55:47 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed
2016-08-12 15:12:59 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed
2016-05-31 17:55:47 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-08-12 15:12:59 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked
2016-05-31 17:55:47 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ
2016-05-31 17:55:47 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions
2016-05-31 17:55:47 +02:00
system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall
2016-08-12 15:12:59 +02:00
system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations
2016-10-14 00:21:40 +02:00
system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute
2016-05-31 17:55:47 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-10-14 00:21:40 +02:00
system.cpu.iew.exec_nop 12823 # number of nop insts executed
system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed
system.cpu.iew.exec_branches 20621332 # Number of branches executed
system.cpu.iew.exec_stores 4915668 # Number of stores executed
system.cpu.iew.exec_rate 0.853083 # Inst execution rate
system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back
system.cpu.iew.wb_producers 59691499 # num instructions producing a value
system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value
system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit
2016-05-31 17:55:47 +02:00
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
2016-10-14 00:21:40 +02:00
system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committedInsts 90602408 # Number of instructions committed
system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27220755 # Number of memory references committed
system.cpu.commit.loads 22475911 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.branches 18732305 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 218887121 # The number of ROB reads
system.cpu.rob.rob_writes 219522508 # The number of ROB writes
system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling
2016-05-31 17:55:47 +02:00
system.cpu.committedInsts 90589799 # Number of Instructions Simulated
system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
2016-10-14 00:21:40 +02:00
system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads
system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 108097860 # number of integer regfile reads
system.cpu.int_regfile_writes 58692141 # number of integer regfile writes
2016-08-12 15:12:59 +02:00
system.cpu.fp_regfile_reads 58 # number of floating regfile reads
system.cpu.fp_regfile_writes 93 # number of floating regfile writes
2016-10-14 00:21:40 +02:00
system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads
system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes
system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads
2016-05-31 17:55:47 +02:00
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 5470621 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits
2016-05-31 17:55:47 +02:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
2016-08-12 15:12:59 +02:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
2016-05-31 17:55:47 +02:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits
system.cpu.dcache.overall_hits::total 18241616 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses
system.cpu.dcache.overall_misses::total 9968629 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks
system.cpu.dcache.writebacks::total 5470621 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses
2016-05-31 17:55:47 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 448 # number of replacements
system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses
system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits
system.cpu.icache.overall_hits::total 32274508 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses
system.cpu.icache.overall_misses::total 1151 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 94.102222 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 126.500000 # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 448 # number of writebacks
system.cpu.icache.writebacks::total 448 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60405484 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 60405484 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60405484 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 60405484 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles
2016-05-31 17:55:47 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 4988856 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 5295771 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 266816 # number of redundant prefetches already in prefetch queue
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.prefetcher.pfSpanPage 14074045 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 140 # number of replacements
system.cpu.l2cache.tags.tagsinuse 11212.925557 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5291618 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 14696 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 360.071992 # Average number of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 58.647341 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.680803 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003580 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.684383 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 60 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 839 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003662 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 180525801 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 180525801 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 5457281 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 5457281 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10913 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 10913 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 226015 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 226015 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 206 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 206 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241513 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 5241513 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 206 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 5467528 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 5467734 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 206 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 5467528 # number of overall hits
system.cpu.l2cache.overall_hits::total 5467734 # number of overall hits
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 505 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 505 # number of ReadExReq misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_misses::cpu.data 3605 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4306 # number of demand (read+write) misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_misses::cpu.data 3605 # number of overall misses
system.cpu.l2cache.overall_misses::total 4306 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 63500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 63500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64129500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 64129500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58109500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 58109500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 616309000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 616309000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 58109500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 680438500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 738548000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 58109500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 680438500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 738548000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457281 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 5457281 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 10913 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 10913 # number of WritebackClean accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 226520 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 226520 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 907 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244613 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 5244613 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 907 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 5471133 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 5472040 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 907 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 5471133 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks
system.cpu.l2cache.writebacks::total 104 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316848 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 320959 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1079223443 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45646000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45646000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53848500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 318864 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks)
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 18190 # Transaction distribution
system.membus.trans_dist::WritebackDirty 104 # Transaction distribution
system.membus.trans_dist::CleanEvict 36 # Transaction distribution
2016-05-31 17:55:47 +02:00
system.membus.trans_dist::UpgradeReq 4 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadExReq 342 # Transaction distribution
system.membus.trans_dist::ReadExResp 342 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.membus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::samples 18537 # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::total 18537 # Request fanout histogram
system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks)
2016-08-12 15:12:59 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
---------- End Simulation Statistics ----------
