2007-04-09 09:59:56 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-05-16 01:25:35 +02:00
|
|
|
global.BPredUnit.BTBHits 2726 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 7230 # Number of BTB lookups
|
2007-04-09 09:59:56 +02:00
|
|
|
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
2007-05-16 01:25:35 +02:00
|
|
|
global.BPredUnit.condIncorrect 2062 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 7954 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 7954 # Number of BP lookups
|
2007-04-09 09:59:56 +02:00
|
|
|
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
2007-05-16 01:25:35 +02:00
|
|
|
host_inst_rate 37089 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 154932 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 0.30 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 53780846 # Simulator tick rate (ticks/s)
|
|
|
|
|
memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
|
2007-04-09 09:59:56 +02:00
|
|
|
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
|
2007-05-16 01:25:35 +02:00
|
|
|
memdepunit.memDep.insertedLoads 3198 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 2970 # Number of stores inserted to the mem dependence unit.
|
2007-04-09 09:59:56 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
sim_insts 10976 # Number of instructions simulated
|
2007-05-16 01:25:35 +02:00
|
|
|
sim_seconds 0.000016 # Number of seconds simulated
|
|
|
|
|
sim_ticks 15931500 # Number of ticks simulated
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:branches 2152 # Number of branches committed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 146 # number cycles where commit BW limit reached
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 28801
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-05-16 01:25:35 +02:00
|
|
|
0 23411 8128.54%
|
|
|
|
|
1 2862 993.72%
|
|
|
|
|
2 1174 407.62%
|
|
|
|
|
3 608 211.10%
|
|
|
|
|
4 359 124.65%
|
|
|
|
|
5 123 42.71%
|
|
|
|
|
6 103 35.76%
|
|
|
|
|
7 15 5.21%
|
|
|
|
|
8 146 50.69%
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.commit.COM:count 10976 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 1462 # Number of loads committed
|
|
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.COM:refs 2760 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 14297 # The number of squashed insts skipped by commit
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.committedInsts 10976 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 10976 # Number of Instructions Simulated
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.cpi 2.903061 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 2.903061 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 2743 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 5392.857143 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4696.969697 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 2659 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 453000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.030623 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 84 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 310000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.024061 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 5505 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4802.325581 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 1092 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 1101000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.154799 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 200 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 114 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 413000 # number of WriteReq MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.avg_refs 24.717105 # Average number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.demand_accesses 4035 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 5471.830986 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 3751 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 1554000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.070384 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 284 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 723000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.037670 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_accesses 4035 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 5471.830986 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_hits 3751 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 1554000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.070384 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 284 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 132 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 723000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.037670 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.tagsinuse 113.439038 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 3757 # Total number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.decode.DECODE:BlockedCycles 4602 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 38937 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 16098 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 7883 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 3063 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 218 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 7954 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 4933 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 14166 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 44421 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 2121 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.249623 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 4933 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 2726 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 1.394081 # Number of inst fetches per cycle
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 31864
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-05-16 01:25:35 +02:00
|
|
|
0 22632 7102.69%
|
|
|
|
|
1 2187 686.35%
|
|
|
|
|
2 562 176.37%
|
|
|
|
|
3 869 272.72%
|
|
|
|
|
4 521 163.51%
|
|
|
|
|
5 770 241.65%
|
|
|
|
|
6 886 278.06%
|
|
|
|
|
7 243 76.26%
|
|
|
|
|
8 3194 1002.39%
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 4933 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 5310.666667 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4396.174863 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 4558 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 1991500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.076019 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 375 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 1609000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.074194 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.avg_refs 12.453552 # Average number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_accesses 4933 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 5310.666667 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 4558 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 1991500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.076019 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 375 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 1609000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.074194 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_accesses 4933 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 5310.666667 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_hits 4558 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 1991500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.076019 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 375 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 9 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 1609000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.074194 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 366 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 1 # number of replacements
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.sampled_refs 366 # Sample count of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.tagsinuse 233.760012 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 4558 # Total number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.idleCycles 499 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 3548 # Number of branches executed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.EXEC:rate 0.670318 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 5385 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 2502 # Number of stores executed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.WB:consumers 10159 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 20199 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.790629 # average fanout of values written-back
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.WB:producers 8032 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.633913 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 20448 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 2568 # Number of branch mispredicts detected at execute
|
2007-04-23 18:13:19 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.iewDispLoadInsts 3198 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 610 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2750 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 2970 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 25274 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 2883 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 21359 # Number of executed instructions
|
2007-04-23 18:13:19 +02:00
|
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 3063 # Number of cycles IEW is squashing
|
2007-04-23 18:13:19 +02:00
|
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 52 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1736 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1672 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 52 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1610 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.344464 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.344464 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 22822 # Type of FU issued
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2007-05-16 01:25:35 +02:00
|
|
|
(null) 1826 8.00% # Type of FU issued
|
|
|
|
|
IntAlu 15247 66.81% # Type of FU issued
|
2007-04-09 09:59:56 +02:00
|
|
|
IntMult 0 0.00% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-05-16 01:25:35 +02:00
|
|
|
MemRead 3042 13.33% # Type of FU issued
|
|
|
|
|
MemWrite 2707 11.86% # Type of FU issued
|
2007-04-09 09:59:56 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst)
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2007-05-16 01:25:35 +02:00
|
|
|
IntAlu 50 26.32% # attempts to use FU when none available
|
2007-04-09 09:59:56 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-05-16 01:25:35 +02:00
|
|
|
MemRead 25 13.16% # attempts to use FU when none available
|
|
|
|
|
MemWrite 115 60.53% # attempts to use FU when none available
|
2007-04-09 09:59:56 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 31864
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-05-16 01:25:35 +02:00
|
|
|
0 22879 7180.20%
|
|
|
|
|
1 3824 1200.10%
|
|
|
|
|
2 1304 409.24%
|
|
|
|
|
3 1251 392.61%
|
|
|
|
|
4 1252 392.92%
|
|
|
|
|
5 751 235.69%
|
|
|
|
|
6 414 129.93%
|
|
|
|
|
7 122 38.29%
|
|
|
|
|
8 67 21.03%
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 0.716231 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 24664 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 22822 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 610 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 11119 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 5685 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4458.171206 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.540856 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 2291500 # number of ReadReq miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses 514 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1220000 # number of ReadReq MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 514 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4458.171206 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 2291500 # number of demand (read+write) miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_misses 514 # number of demand (read+write) misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 1220000 # number of demand (read+write) MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 514 # number of demand (read+write) MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 514 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4458.171206 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 2291500 # number of overall miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_misses 514 # number of overall misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 1220000 # number of overall MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses 514 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 514 # Sample count of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 345.564898 # Cycle average of tags in use
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.numCycles 31864 # number of cpu cycles simulated
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.rename.RENAME:IdleCycles 16082 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 44650 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 29655 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 24195 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 7618 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 3063 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:SquashedInsts 8815 # Number of squashed instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 684 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 14327 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 3915 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 631 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 4702 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 623 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
