Update refs for CPU clock changes and O3 CPI/IPC calculation updates.
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/mips/linux/simple-timing/config.out:
tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-timing/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out:
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr:
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout:
Update refs.
--HG--
extra : convert_revision : 34a0d18f213386700e2acdd1eb9ebc5fa6daa7f5
This commit is contained in:
Kevin Lim
parent
dbc1edd23d
commit
46f6fa8b45
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@ -1,50 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
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||||
max_tick=0
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||||
output_file=cout
|
||||
progress_interval=0
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||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
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||||
print_fetchseq=false
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||||
print_iregs=false
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||||
print_opclass=true
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||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
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||||
|
||||
[serialize]
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||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
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||||
mysql_db=
|
||||
mysql_host=
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||||
mysql_password=
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||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
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||||
simulation_sample=0
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||||
text_compat=true
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||||
text_file=m5stats.txt
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||||
dummy=0
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||||
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||||
[system]
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||||
type=System
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||||
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|
@ -55,7 +12,7 @@ physmem=system.physmem
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|||
[system.cpu]
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||||
type=AtomicSimpleCPU
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children=workload
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||||
clock=1
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||||
clock=500
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cpu_id=0
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defer_registration=false
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function_trace=false
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||||
|
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@ -64,7 +21,7 @@ max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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||||
max_loads_any_thread=0
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||||
mem=system.physmem
|
||||
phase=0
|
||||
progress_interval=0
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||||
simulate_stalls=false
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||||
system=system
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||||
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@ -76,6 +33,7 @@ icache_port=system.membus.port[1]
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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||||
cwd=
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egid=100
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env=
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euid=100
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@ -92,6 +50,7 @@ uid=100
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type=Bus
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bus_id=0
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clock=1000
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responder_set=false
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width=64
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port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
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@ -100,14 +59,6 @@ type=PhysicalMemory
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file=
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latency=1
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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[trace]
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bufsize=0
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cycle=0
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dump_on_exit=false
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file=cout
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flags=
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ignore=
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start=0
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||||
|
|
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|||
|
|
@ -1,15 +1,13 @@
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[root]
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type=Root
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||||
clock=1000000000000
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||||
max_tick=0
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progress_interval=0
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output_file=cout
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dummy=0
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||||
|
||||
[system.physmem]
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type=PhysicalMemory
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file=
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range=[0,134217727]
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latency=1
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zero=false
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[system]
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type=System
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@ -21,6 +19,7 @@ type=Bus
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bus_id=0
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clock=1000
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width=64
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responder_set=false
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|
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[system.cpu.workload]
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type=LiveProcess
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||||
|
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@ -29,6 +28,7 @@ executable=tests/test-progs/hello/bin/mips/linux/hello
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input=cin
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output=cout
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env=
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cwd=
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system=system
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uid=100
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euid=100
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|
|
@ -44,64 +44,14 @@ max_insts_all_threads=0
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max_loads_any_thread=0
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max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
mem=system.physmem
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
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clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
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||||
cycle=0
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||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
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||||
print_cycle=true
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||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
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||||
trace_system=client
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||||
|
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[debug]
|
||||
break_cycles=
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||||
|
||||
[statsreset]
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||||
reset_cycle=0
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||||
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@ -1,13 +1,13 @@
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|||
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||||
---------- Begin Simulation Statistics ----------
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host_inst_rate 52255 # Simulator instruction rate (inst/s)
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host_mem_usage 148024 # Number of bytes of host memory used
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host_seconds 0.11 # Real time elapsed on the host
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host_tick_rate 52038 # Simulator tick rate (ticks/s)
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host_inst_rate 7127 # Simulator instruction rate (inst/s)
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host_mem_usage 148488 # Number of bytes of host memory used
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host_seconds 0.79 # Real time elapsed on the host
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host_tick_rate 3561193 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5657 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 5656 # Number of ticks simulated
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sim_seconds 0.000003 # Number of seconds simulated
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sim_ticks 2828000 # Number of ticks simulated
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 5657 # number of cpu cycles simulated
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@ -6,8 +6,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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||||
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M5 compiled Oct 9 2006 19:28:25
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M5 started Mon Oct 9 19:28:56 2006
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M5 executing on zizzer.eecs.umich.edu
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command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
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Exiting @ tick 5656 because target called exit()
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M5 compiled Apr 22 2007 20:47:32
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M5 started Sun Apr 22 20:47:35 2007
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M5 executing on zamp.eecs.umich.edu
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command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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Exiting @ tick 2828000 because target called exit()
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@ -1,50 +1,7 @@
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[root]
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type=Root
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||||
children=system
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||||
checkpoint=
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clock=1000000000000
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max_tick=0
|
||||
output_file=cout
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||||
progress_interval=0
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||||
|
||||
[debug]
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||||
break_cycles=
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[exetrace]
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intel_format=false
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||||
pc_symbol=true
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||||
print_cpseq=false
|
||||
print_cycle=true
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||||
print_data=true
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||||
print_effaddr=true
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||||
print_fetchseq=false
|
||||
print_iregs=false
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||||
print_opclass=true
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print_thread=true
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speculative=true
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trace_system=client
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[serialize]
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count=10
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||||
cycle=0
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||||
dir=cpt.%012d
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period=0
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[stats]
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||||
descriptions=true
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||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
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||||
ignore_events=
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||||
mysql_db=
|
||||
mysql_host=
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||||
mysql_password=
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||||
mysql_user=
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||||
project_name=test
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||||
simulation_name=test
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||||
simulation_sample=0
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||||
text_compat=true
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||||
text_file=m5stats.txt
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||||
dummy=0
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||||
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||||
[system]
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||||
type=System
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||||
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|
@ -55,7 +12,7 @@ physmem=system.physmem
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|||
[system.cpu]
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||||
type=TimingSimpleCPU
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||||
children=dcache icache l2cache toL2Bus workload
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||||
clock=1
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||||
clock=500
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||||
cpu_id=0
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||||
defer_registration=false
|
||||
function_trace=false
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||||
|
|
@ -64,7 +21,7 @@ max_insts_all_threads=0
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|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
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||||
phase=0
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||||
progress_interval=0
|
||||
system=system
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||||
workload=system.cpu.workload
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||||
|
|
@ -78,7 +35,6 @@ assoc=2
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|||
block_size=64
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||||
compressed_bus=false
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||||
compression_latency=0
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||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
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||||
latency=1
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||||
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@ -118,7 +74,6 @@ assoc=2
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|||
block_size=64
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||||
compressed_bus=false
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||||
compression_latency=0
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||||
do_copy=false
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||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -158,7 +113,6 @@ assoc=2
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|||
block_size=64
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||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -195,12 +149,14 @@ mem_side=system.membus.port[1]
|
|||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -217,6 +173,7 @@ uid=100
|
|||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -225,14 +182,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -21,10 +19,52 @@ type=Bus
|
|||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/mips/linux/hello
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -32,7 +72,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -61,48 +100,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/mips/linux/hello
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
mem=system.cpu.dcache
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -110,7 +110,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -149,7 +148,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -178,53 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 57798 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179040 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 17679602 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 224031 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153864 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 205051803 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5657 # Number of instructions simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1738011 # Number of ticks simulated
|
||||
sim_seconds 0.000005 # Number of seconds simulated
|
||||
sim_ticks 5264500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3987.109756 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2987.109756 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3762.195122 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2762.195122 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 326943 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 308500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 244943 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 226500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3968.740000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2968.740000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3690 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2690 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 198437 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 184500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 148437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 134500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3980.151515 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3734.848485 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 525380 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 493000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 393380 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 361000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3980.151515 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3734.848485 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1922 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 525380 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 493000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 132 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 393380 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 361000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 82.396200 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 86.050916 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3978.069307 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2978.069307 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3740.924092 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2740.924092 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1205355 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1133500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 902355 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 830500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3978.069307 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3740.924092 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1205355 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1133500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 902355 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 830500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3978.069307 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3740.924092 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5355 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1205355 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1133500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 303 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 902355 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 830500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 133.062649 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 137.160443 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2983.237875 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1982.237875 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2743.648961 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1742.648961 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1291742 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1188000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 858309 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 754567 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2983.237875 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2743.648961 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1291742 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1188000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 858309 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 754567 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2983.237875 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2743.648961 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1291742 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1188000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 433 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 858309 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 754567 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 216.976175 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 224.535228 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1738011 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5264500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5657 # Number of instructions executed
|
||||
system.cpu.num_refs 2055 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -6,8 +6,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 13 2006 18:43:33
|
||||
M5 started Fri Oct 13 18:44:16 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
|
||||
Exiting @ tick 1738011 because target called exit()
|
||||
M5 compiled Apr 22 2007 20:47:32
|
||||
M5 started Sun Apr 22 20:47:36 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 5264500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,50 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -55,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -64,7 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.physmem
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
|
|
@ -76,6 +33,7 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -92,6 +50,7 @@ uid=100
|
|||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
|
|
@ -100,14 +59,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -21,6 +19,7 @@ type=Bus
|
|||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
@ -29,6 +28,7 @@ executable=tests/test-progs/hello/bin/sparc/linux/hello
|
|||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -44,64 +44,14 @@ max_insts_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
mem=system.physmem
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 58121 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148396 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 57840 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 16183 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 149132 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_tick_rate 8071210 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4863 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 4862 # Number of ticks simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 2431000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4863 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -5,8 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 27 2006 02:07:29
|
||||
M5 started Fri Oct 27 02:08:08 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
|
||||
Exiting @ tick 4862 because target called exit()
|
||||
M5 compiled Apr 22 2007 20:15:56
|
||||
M5 started Sun Apr 22 20:26:04 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2431000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,50 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -55,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
@ -64,7 +21,7 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
workload=system.cpu.workload
|
||||
|
|
@ -192,12 +149,14 @@ mem_side=system.membus.port[1]
|
|||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
|
|
@ -214,6 +173,7 @@ uid=100
|
|||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -222,14 +182,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
dummy=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -21,10 +19,52 @@ type=Bus
|
|||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/sparc/linux/hello
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -60,48 +100,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/sparc/linux/hello
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
mem=system.cpu.dcache
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -175,53 +176,3 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 158849 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179428 # Number of bytes of host memory used
|
||||
host_inst_rate 189060 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154496 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 50697812 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 164285984 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4863 # Number of instructions simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1573001 # Number of ticks simulated
|
||||
sim_seconds 0.000004 # Number of seconds simulated
|
||||
sim_ticks 4347500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3971.370370 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2971.370370 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3740.740741 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2740.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 214454 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 202000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 160454 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 148000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3981.559524 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2981.559524 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3625 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2625 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 334451 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 304500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 250451 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 220500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3977.572464 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3670.289855 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 548905 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 506500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 410905 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 368500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3670.289855 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1131 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 506500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 138 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 410905 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 368500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 81.997528 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 84.314216 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3977.960938 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.960938 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3796.875000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2796.875000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1018358 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 972000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 762358 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 716000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3977.960938 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3796.875000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1018358 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 972000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 762358 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 716000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3796.875000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 4608 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 972000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 256 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 762358 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 716000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 114.778311 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 114.238100 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2760.869565 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1759.869565 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1079500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 688109 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2760.869565 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1079500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 688109 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2760.869565 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1079500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 391 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 688109 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 197.030867 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1573001 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4347500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 4863 # Number of instructions executed
|
||||
system.cpu.num_refs 1269 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -5,8 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 27 2006 02:07:29
|
||||
M5 started Fri Oct 27 02:08:11 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
|
||||
Exiting @ tick 1573001 because target called exit()
|
||||
M5 compiled Apr 22 2007 20:15:56
|
||||
M5 started Sun Apr 22 20:26:05 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 4347500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ activity=0
|
|||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
clock=500
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
numThreads=1
|
||||
cpu_id=0
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 2990 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 7055 # Number of BTB lookups
|
||||
global.BPredUnit.BTBHits 3154 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 9574 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 2077 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 7846 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 7846 # Number of BP lookups
|
||||
global.BPredUnit.condIncorrect 2047 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 10459 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 10459 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 15119 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154868 # Number of bytes of host memory used
|
||||
host_seconds 0.73 # Real time elapsed on the host
|
||||
host_tick_rate 1956796 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
|
||||
host_inst_rate 26468 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154944 # Number of bytes of host memory used
|
||||
host_seconds 0.41 # Real time elapsed on the host
|
||||
host_tick_rate 32157366 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 3250 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 2817 # Number of stores inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedLoads 3573 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 3440 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 10976 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 1421211 # Number of ticks simulated
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
sim_ticks 13345500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 2152 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 172 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 221349
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 23147
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 215844 9751.30%
|
||||
1 2970 134.18%
|
||||
2 1290 58.28%
|
||||
3 631 28.51%
|
||||
4 208 9.40%
|
||||
5 90 4.07%
|
||||
6 133 6.01%
|
||||
7 11 0.50%
|
||||
8 172 7.77%
|
||||
0 17950 7754.78%
|
||||
1 2912 1258.05%
|
||||
2 993 429.00%
|
||||
3 424 183.18%
|
||||
4 287 123.99%
|
||||
5 235 101.53%
|
||||
6 103 44.50%
|
||||
7 79 34.13%
|
||||
8 164 70.85%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2760 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 2077 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 2047 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 14263 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 18321 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 10976 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 10976 # Number of Instructions Simulated
|
||||
system.cpu.cpi 129.483509 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 129.483509 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2737 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 6585.044776 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6511.939394 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2603 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 882396 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.048959 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 429788 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.024114 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 2.431851 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.431851 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2813 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 4311.764706 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3546.153846 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2728 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 366500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.030217 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 85 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 230500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.023107 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 7960.583924 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7136.918605 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 869 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 3367327 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.327399 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 423 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 337 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 613775 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 4645.408163 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3470.930233 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1096 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 910500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.151703 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 196 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 110 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 298500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 22.881579 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 25.364238 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 4029 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7629.664273 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 6865.546053 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3472 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4249723 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.138248 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 405 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1043563 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.037726 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 4105 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4544.483986 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3824 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1277000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.068453 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 281 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 529000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.036784 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 4029 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7629.664273 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 6865.546053 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 4105 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4544.483986 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 3472 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4249723 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.138248 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 557 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 405 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1043563 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.037726 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 3824 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1277000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.068453 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 281 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 130 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 529000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.036784 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 90.938737 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3478 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 112.362185 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 192719 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 39774 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 20128 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 8238 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 3162 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 264 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 7846 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 5085 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 14399 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 745 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 43304 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2134 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.034947 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 5085 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 2990 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.192881 # Number of inst fetches per cycle
|
||||
system.cpu.decode.DECODE:BlockedCycles 4942 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 48420 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 8618 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 9347 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 3545 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 240 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 10459 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 5440 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 16262 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 55152 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2110 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.391840 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 5440 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 3154 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.066237 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 224511
|
||||
system.cpu.fetch.rateDist.samples 26692
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 215198 9585.19%
|
||||
1 2258 100.57%
|
||||
2 627 27.93%
|
||||
3 958 42.67%
|
||||
4 553 24.63%
|
||||
5 816 36.35%
|
||||
6 951 42.36%
|
||||
7 280 12.47%
|
||||
8 2870 127.83%
|
||||
0 15871 5945.98%
|
||||
1 2250 842.95%
|
||||
2 637 238.65%
|
||||
3 971 363.78%
|
||||
4 550 206.05%
|
||||
5 848 317.70%
|
||||
6 962 360.41%
|
||||
7 321 120.26%
|
||||
8 4282 1604.23%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 5085 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5148.266776 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4502.972752 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4474 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3145591 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.120157 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 611 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 244 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1652591 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.072173 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 5440 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3939.473684 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2944.591029 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5060 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1497000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.069853 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 380 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1116000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.069669 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 12.325069 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 13.350923 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5085 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5148.266776 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4502.972752 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4474 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3145591 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.120157 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 611 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 244 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1652591 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.072173 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 5440 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3939.473684 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5060 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1497000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.069853 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 380 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1116000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.069669 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 379 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5085 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5148.266776 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4502.972752 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 5440 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3939.473684 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 4474 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3145591 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.120157 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 611 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 244 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1652591 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.072173 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 367 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 5060 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1497000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.069853 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 380 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1116000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.069669 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 379 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -215,61 +215,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 363 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 379 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 172.869174 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4474 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 242.916499 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5060 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1196701 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 3576 # Number of branches executed
|
||||
system.cpu.iew.EXEC:branches 3713 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.092548 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 5257 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2386 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 0.830061 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 5553 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2589 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 9737 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 19769 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.790901 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 10966 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 21367 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.799836 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 7701 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.088054 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 20061 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2593 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 476 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 3250 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 617 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2705 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 2817 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 25240 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2871 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1780 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 20778 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 8771 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.800502 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 21712 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2654 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 3573 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 630 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 1509 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 3440 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 29298 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2964 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3437 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 22156 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 3162 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 3545 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1788 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1519 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1631 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.007723 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.007723 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 22558 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 75 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2111 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 2142 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 75 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1624 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.411209 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.411209 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 25593 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 1831 8.12% # Type of FU issued
|
||||
IntAlu 15054 66.73% # Type of FU issued
|
||||
(null) 1919 7.50% # Type of FU issued
|
||||
IntAlu 17231 67.33% # Type of FU issued
|
||||
IntMult 0 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
|
|
@ -278,16 +277,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 3091 13.70% # Type of FU issued
|
||||
MemWrite 2582 11.45% # Type of FU issued
|
||||
MemRead 3429 13.40% # Type of FU issued
|
||||
MemWrite 3014 11.78% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.007181 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 238 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009299 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 42 25.93% # attempts to use FU when none available
|
||||
IntAlu 99 41.60% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -296,43 +295,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 14 8.64% # attempts to use FU when none available
|
||||
MemWrite 106 65.43% # attempts to use FU when none available
|
||||
MemRead 22 9.24% # attempts to use FU when none available
|
||||
MemWrite 117 49.16% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 224511
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 26692
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 215315 9590.40%
|
||||
1 4124 183.69%
|
||||
2 1297 57.77%
|
||||
3 1306 58.17%
|
||||
4 1190 53.00%
|
||||
5 707 31.49%
|
||||
6 433 19.29%
|
||||
7 83 3.70%
|
||||
8 56 2.49%
|
||||
0 17644 6610.22%
|
||||
1 3262 1222.09%
|
||||
2 1371 513.64%
|
||||
3 1071 401.24%
|
||||
4 1568 587.44%
|
||||
5 925 346.55%
|
||||
6 579 216.92%
|
||||
7 171 64.06%
|
||||
8 101 37.84%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.100476 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 24623 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 22558 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 11469 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 174 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 290 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 5834 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 513 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4754.779727 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2343.506823 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2439202 # number of ReadReq miss cycles
|
||||
system.cpu.iq.ISSUE:rate 0.958827 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 28668 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 25593 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 630 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 15737 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 303 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 526 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3018.060837 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1812.857414 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1587500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 513 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1202219 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_misses 526 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 953563 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 513 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 526 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
|
|
@ -341,32 +340,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
|
|||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4754.779727 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2343.506823 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 526 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3018.060837 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2439202 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1587500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 513 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 526 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1202219 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 953563 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 513 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 526 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4754.779727 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2343.506823 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 526 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3018.060837 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2439202 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1587500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 513 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses 526 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1202219 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 953563 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 513 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 526 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -379,32 +378,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 512 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 526 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 262.946375 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 353.661697 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 224511 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 960 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 26692 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 20098 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 481 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 46931 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 31260 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 25831 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 7921 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 3162 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:SquashedInsts 8042 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.RENAME:UnblockCycles 1212 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 15963 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 190573 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 638 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 5594 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 629 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IdleCycles 8631 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 59097 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 39751 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 31999 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 9086 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 3545 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:SquashedInsts 8167 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.RENAME:UnblockCycles 716 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 22131 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 4224 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 665 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4954 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 658 # count of temporary serializing insts renamed
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -16,9 +16,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 9 2007 03:06:26
|
||||
M5 started Mon Apr 9 03:06:54 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
M5 compiled Apr 22 2007 20:15:56
|
||||
M5 started Sun Apr 22 20:26:05 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1421211 because target called exit()
|
||||
Exiting @ tick 13345500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 65718 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179556 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_tick_rate 65601 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 430012 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 149064 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 207711772 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 11001 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 11000 # Number of ticks simulated
|
||||
sim_seconds 0.000005 # Number of seconds simulated
|
||||
sim_ticks 5500000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 11001 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -16,9 +16,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 29 2007 15:29:35
|
||||
M5 started Thu Mar 29 15:39:35 2007
|
||||
M5 executing on zeep
|
||||
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
|
||||
M5 compiled Apr 22 2007 20:15:56
|
||||
M5 started Sun Apr 22 20:26:06 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 11000 because target called exit()
|
||||
Exiting @ tick 5500000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ physmem=system.physmem
|
|||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ progress_interval=0
|
|||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
clock=500
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 39129 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153232 # Number of bytes of host memory used
|
||||
host_seconds 0.28 # Real time elapsed on the host
|
||||
host_tick_rate 6030675 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 285170 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 154424 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 211576923 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 11001 # Number of instructions simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1698003 # Number of ticks simulated
|
||||
sim_seconds 0.000008 # Number of seconds simulated
|
||||
sim_ticks 8251500 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3977.759259 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2977.759259 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3712.962963 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2712.962963 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 214799 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 200500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 160799 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 146500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3963.647727 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2963.647727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3676.136364 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2676.136364 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1204 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 348801 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 323500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.068111 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 88 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 260801 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 235500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.068111 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 88 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3969.014085 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2969.014085 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3690.140845 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2612 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 563600 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 524000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.051561 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 421600 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 382000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.051561 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3969.014085 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2969.014085 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3690.140845 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2612 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 563600 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 524000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.051561 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 142 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 421600 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 382000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.051561 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 86.872921 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 106.692969 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3961.367491 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2961.367491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3743.816254 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2743.816254 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1121067 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1059500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 838067 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 776500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3961.367491 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2961.367491 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3743.816254 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1121067 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1059500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 283 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 838067 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 776500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3961.367491 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2961.367491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3743.816254 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 10719 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1121067 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1059500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 283 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 838067 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 776500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 125.297191 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 170.449932 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 10719 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 423 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2968.515366 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1967.515366 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1255682 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2730.496454 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1729.496454 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1155000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 423 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 832259 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 731577 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 423 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2968.515366 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1967.515366 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2730.496454 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1255682 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1155000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 832259 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 731577 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 423 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2968.515366 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1967.515366 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2730.496454 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1255682 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1155000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 423 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 832259 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 731577 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 423 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 211.742547 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 276.385948 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1698003 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 8251500 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 11001 # Number of instructions executed
|
||||
system.cpu.num_refs 2760 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
warn: More than two loadable segments in ELF object.
|
||||
warn: Ignoring segment @ 0x0 length 0x0.
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -16,9 +16,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2007 05:25:15
|
||||
M5 started Sun Apr 8 22:54:12 2007
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
M5 compiled Apr 22 2007 20:15:56
|
||||
M5 started Sun Apr 22 20:26:07 2007
|
||||
M5 executing on zamp.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1698003 because target called exit()
|
||||
Exiting @ tick 8251500 because target called exit()
|
||||
|
|
|
|||
Loading…
Reference in a new issue