2006-08-17 00:48:15 +02:00
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|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2007-05-16 01:25:35 +02:00
|
|
|
host_inst_rate 228404 # Simulator instruction rate (inst/s)
|
2007-04-22 20:50:37 +02:00
|
|
|
host_mem_usage 153176 # Number of bytes of host memory used
|
2007-05-16 01:25:35 +02:00
|
|
|
host_seconds 0.01 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 552831639 # Simulator tick rate (ticks/s)
|
2006-08-17 00:48:15 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
sim_insts 2578 # Number of instructions simulated
|
2007-05-16 01:25:35 +02:00
|
|
|
sim_seconds 0.000006 # Number of seconds simulated
|
|
|
|
|
sim_ticks 6472000 # Number of ticks simulated
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.overall_hits 627 # number of overall hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.overall_misses 82 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.overall_hits 2416 # number of overall hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 163 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2006-08-17 00:48:15 +02:00
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 245 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2006-08-17 00:48:15 +02:00
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.numCycles 6472000 # number of cpu cycles simulated
|
2006-08-17 00:48:15 +02:00
|
|
|
system.cpu.num_insts 2578 # Number of instructions executed
|
|
|
|
|
system.cpu.num_refs 710 # Number of memory references
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
