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gem5/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini

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tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[root]
type=Root
children=system
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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full_system=false
stats: update stats for cache occupancy and clock domain changes
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sim_quantum=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
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children=clk_domain cpu dvfs_handler membus monitor physmem
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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init_param=0
kernel=
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
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kernel_addr_check=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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load_addr_mask=1099511627775
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
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load_offset=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]
[system.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
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domain_id=-1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.clk_domain.voltage_domain
[system.clk_domain.voltage_domain]
type=VoltageDomain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
[system.cpu]
type=TrafficGen
clk_domain=system.clk_domain
config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg
elastic_req=false
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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system=system
port=system.monitor.slave
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.membus]
stats: updates due to changes to x86, stale configs.
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type=NoncoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
header_cycles=1
use_default_range=false
width=16
master=system.physmem.port
slave=system.monitor.master system.system_port
[system.monitor]
type=CommMonitor
bandwidth_bins=20
burst_length_bins=20
clk_domain=system.clk_domain
disable_addr_dists=true
disable_bandwidth_hists=false
disable_burst_length_hists=false
disable_itt_dists=false
disable_latency_hists=false
disable_outstanding_hists=false
disable_transaction_hists=false
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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itt_bins=20
itt_max_bin=100000
latency_bins=20
outstanding_bins=20
read_addr_mask=18446744073709551615
sample_period=1000000000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
system=system
trace_compress=true
trace_enable=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
trace_file=monitor.ptrc.gz
transaction_bins=20
write_addr_mask=18446744073709551615
master=system.membus.slave[0]
slave=system.cpu.port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:134217727
port=system.membus.master[0]
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