2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.110281 # Number of seconds simulated
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sim_ticks 110281184000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-07-10 19:56:09 +02:00
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host_inst_rate 65382 # Simulator instruction rate (inst/s)
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host_tick_rate 38217412 # Simulator tick rate (ticks/s)
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host_mem_usage 261804 # Number of bytes of host memory used
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host_seconds 2885.63 # Real time elapsed on the host
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sim_insts 188667677 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 400 # Number of system calls
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2011-07-10 19:56:09 +02:00
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system.cpu.numCycles 220562369 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.lookups 104258409 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 82362571 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 9936095 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 86105898 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 80445450 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.usedRAS 4758962 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 112969 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 46358647 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 433367935 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 104258409 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 85204412 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 111822484 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 35665794 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 36992864 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps
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system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
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system.cpu.fetch.CacheLines 42110119 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 2232853 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 220504638 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.132131 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.672325 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::0 108888253 49.38% 49.38% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4953673 2.25% 51.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 33070296 15.00% 66.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 18447401 8.37% 74.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 9377183 4.25% 79.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 12785261 5.80% 85.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 8550568 3.88% 88.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 4486115 2.03% 90.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 19945888 9.05% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::total 220504638 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.472694 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.964832 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 55339748 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 35376598 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 103212898 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1403307 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 25172087 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 14322485 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 170339 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 440125451 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 696276 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 25172087 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 64672455 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 776963 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 29575154 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 95204893 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 5103086 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 403993606 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 69868 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 2710880 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 687477122 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 1728388844 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1709997227 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 18391617 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 298062016 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 389415097 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 2865354 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 2816189 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 26097925 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 51690689 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 18730866 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 8573671 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 5359744 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 346939727 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 2374386 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 267717167 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 907172 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 158256505 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 384971202 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 738758 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 220504638 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.214111 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.476414 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::0 103384796 46.89% 46.89% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 39397520 17.87% 64.75% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 35187917 15.96% 80.71% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 23179085 10.51% 91.22% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 11803879 5.35% 96.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 4771097 2.16% 98.74% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 2229685 1.01% 99.75% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 447825 0.20% 99.95% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 102834 0.05% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::total 220504638 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IntAlu 341650 17.75% 17.75% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 6050 0.31% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 35 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 4 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 93 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.07% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1226198 63.72% 81.79% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 350464 18.21% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 208615296 77.92% 77.92% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 925342 0.35% 78.27% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.27% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 6202 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 33026 0.01% 78.28% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.28% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 166299 0.06% 78.35% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 260522 0.10% 78.44% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 76108 0.03% 78.47% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 471200 0.18% 78.65% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 207528 0.08% 78.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71629 0.03% 78.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 327 0.00% 78.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 42633393 15.92% 94.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 14250295 5.32% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 267717167 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.213793 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 1924494 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.007189 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 754979573 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 505620151 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 248098864 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 3791065 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 2339721 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1843061 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 267732701 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 1908960 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 1050657 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 21838970 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7625 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 472350 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 6083999 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 25172087 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 44760 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 3320 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 349368262 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 3978827 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 51690689 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 18730866 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 2350473 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 564 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 2427 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 472350 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 10008076 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1698961 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 11707037 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 254915521 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 40541135 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 12801646 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_nop 54149 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 54377446 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 53214768 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 13836311 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.155753 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 251638468 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 249941925 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 151812393 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 254020317 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.133203 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.597639 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 188682065 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 160676887 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 1635628 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 9797761 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 195332552 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.965953 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.628775 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 109939001 56.28% 56.28% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 42858902 21.94% 78.22% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 20127469 10.30% 88.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 8563678 4.38% 92.91% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 5111696 2.62% 95.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 2060801 1.06% 96.58% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 1694385 0.87% 97.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 852868 0.44% 97.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 4123752 2.11% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 195332552 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 188682065 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.refs 42498585 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 29851718 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 22408 # Number of memory barriers committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branches 40283916 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.int_insts 150115157 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 4123752 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.rob.rob_reads 540562551 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 723954086 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1712 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 57731 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 188667677 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 188667677 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 1.169052 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.169052 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.855394 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.855394 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 1139481673 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 415646596 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 2922802 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 2492399 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 524104390 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 824502 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 1939 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1330.149475 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 42105837 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 3648 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 11542.170230 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1330.149475 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.649487 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 42105837 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 42105837 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 42105837 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 4282 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 4282 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 4282 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 102623500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 102623500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 102623500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 42110119 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 42110119 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 42110119 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 23966.254087 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 23966.254087 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 23966.254087 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 634 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 634 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 634 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 3648 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 3648 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 3648 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 74999500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 74999500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 74999500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20559.073465 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.replacements 53 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 1408.348450 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 51108076 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1850 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 27625.987027 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 1408.348450 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.343835 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 38699028 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 27661 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 24640 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 51055775 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 51055775 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1814 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_misses 9354 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 9354 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 59541500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 236790000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 296331500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 296331500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 38700842 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 27663 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 24640 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 51065129 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 51065129 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.000183 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000183 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 32823.318633 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 31404.509284 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 31679.655762 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 31679.655762 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks 17 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 6451 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 7504 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 7504 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1089 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 1850 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 1850 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 24275500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 38318500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 62594000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 62594000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31899.474376 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35186.868687 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 1929.340531 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2692 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.635587 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 1926.279074 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 3.061457 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.058785 # Average percentage of cache occupancy
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 1719 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 1719 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2698 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 3779 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 3779 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 92484500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 37157500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 129642000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 129642000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 4409 # number of ReadReq accesses(hits+misses)
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1089 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 5498 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 5498 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.611930 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.992654 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.687341 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.687341 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34278.910304 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34373.265495 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34305.901032 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34305.901032 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2683 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 3764 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 3764 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 83387000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33564500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 116951500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 116951500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608528 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992654 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.684613 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.684613 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.761461 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.491212 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
