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Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Updated Authors from bk prs info --HG-- extra : convert_revision : 77f475b156d81c03a2811818fa23593d5615c685
2006-06-01 01:26:56 +02:00
*
* Authors: Gabe Black
* Korey Sewell
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
*/
"sparc" -> "mips" arch/mips/isa_desc/formats.h: arch/mips/isa_desc/formats/basic.format: arch/mips/isa_desc/formats/branch.format: arch/mips/isa_desc/formats/integerop.format: arch/mips/isa_desc/formats/mem.format: arch/mips/isa_desc/formats/noop.format: arch/mips/isa_desc/formats/trap.format: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: changing "sparc" strings to "mips" everywhere --HG-- extra : convert_revision : eaecf9eeac26e3ef0726deef2fb5d7e9ad172984
2006-01-26 22:19:44 +01:00
#include "arch/mips/isa_traits.hh"
Mips Code Cleanup: Fix some author stuff and copyright dates Take out full system code src/arch/mips/isa/base.isa: src/arch/mips/isa/bitfields.isa: copyright info src/arch/mips/isa/decoder.isa: src/arch/mips/isa/formats/basic.isa: src/arch/mips/isa/formats/branch.isa: src/arch/mips/isa/formats/control.isa: src/arch/mips/isa/formats/fp.isa: src/arch/mips/isa/formats/int.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/noop.isa: src/arch/mips/isa/formats/tlbop.isa: src/arch/mips/isa/formats/trap.isa: src/arch/mips/isa/formats/unimp.isa: src/arch/mips/isa/formats/unknown.isa: src/arch/mips/isa/formats/util.isa: src/arch/mips/isa/includes.isa: src/arch/mips/isa/main.isa: src/arch/mips/isa/operands.isa: src/arch/mips/process.cc: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/stacktrace.hh: copyright 2006 src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: copyright 2006 take out full system src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/regfile.hh: copyright 2006 use FloatRegVal src/arch/mips/regfile/int_regfile.hh: copyright 2006 move HI/LO to types.hh src/arch/mips/types.hh: copyright 2006 typedef FloatRegVal --HG-- extra : convert_revision : 1d0d72cd655a4e28622745a6c6b06349da533a1d
2006-06-15 07:00:15 +02:00
//#include "config/full_system.hh"
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
#include "cpu/static_inst.hh"
#include "sim/serialize.hh"
Redo the FloatRegFile using unsigned integers Edit the convert_and_round function which access FloatRegFile arch/isa_parser.py: recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately arch/mips/isa/decoder.isa: Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the bit manipulation ourselves. We can just concern ourselves with values. Use unsigned double to get movd... arch/mips/isa/formats/fp.isa: float debug statement arch/mips/isa_traits.cc: add different versions of convert_and_round functions arch/mips/isa_traits.hh: Use an array of uint32_t unsigned integers to represent the Floating Point Regfile configs/test/hello_mips: basic FP program cpu/simple/cpu.hh: spacing --HG-- extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
2006-05-03 02:05:16 +02:00
#include "base/bitfield.hh"
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
Renaming alpha files and changing some MIPS stuff to be more like Alpha version SConscript: changed the alpha_memory.hh to memory.hh in SConscript arch/isa_parser.py: temporarily comment out o3 model arch/mips/isa/base.isa: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: Fix Up Base Class to mirror how Alpha generates StaticInsts arch/mips/faults.cc: MIPS fault.cc file arch/mips/faults.hh: MIPS fault.hh file --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-22 04:02:05 +01:00
using namespace MipsISA;
Redo the FloatRegFile using unsigned integers Edit the convert_and_round function which access FloatRegFile arch/isa_parser.py: recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately arch/mips/isa/decoder.isa: Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the bit manipulation ourselves. We can just concern ourselves with values. Use unsigned double to get movd... arch/mips/isa/formats/fp.isa: float debug statement arch/mips/isa_traits.cc: add different versions of convert_and_round functions arch/mips/isa_traits.hh: Use an array of uint32_t unsigned integers to represent the Floating Point Regfile configs/test/hello_mips: basic FP program cpu/simple/cpu.hh: spacing --HG-- extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
2006-05-03 02:05:16 +02:00
using namespace std;
First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined arch/mips/SConscript: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: arch/mips/process.cc: arch/mips/linux/linux.cc: arch/mips/utility.hh: arch/mips/linux/process.cc: arch/mips/int_regfile.hh: arch/mips/misc_regfile.hh: arch/mips/regfile.hh: arch/mips/types.hh: MIPS directory rearranging --HG-- rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
2006-05-08 00:50:41 +02:00
void
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
2006-06-06 23:32:21 +02:00
MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined arch/mips/SConscript: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: arch/mips/process.cc: arch/mips/linux/linux.cc: arch/mips/utility.hh: arch/mips/linux/process.cc: arch/mips/int_regfile.hh: arch/mips/misc_regfile.hh: arch/mips/regfile.hh: arch/mips/types.hh: MIPS directory rearranging --HG-- rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
2006-05-08 00:50:41 +02:00
{
Merging in a month of changes src/arch/isa_parser.py: Sign extend bit if you read int reg that is greater than default size src/arch/mips/SConscript: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa/base.isa: src/arch/mips/isa/bitfields.isa: src/arch/mips/isa/decoder.isa: src/arch/mips/isa/formats/basic.isa: src/arch/mips/isa/formats/branch.isa: src/arch/mips/isa/formats/formats.isa: src/arch/mips/isa/formats/fp.isa: src/arch/mips/isa/formats/int.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/noop.isa: src/arch/mips/isa/formats/tlbop.isa: src/arch/mips/isa/formats/trap.isa: src/arch/mips/isa/formats/unimp.isa: src/arch/mips/isa/formats/unknown.isa: src/arch/mips/isa/formats/util.isa: src/arch/mips/isa/includes.isa: src/arch/mips/isa/main.isa: src/arch/mips/isa/operands.isa: src/arch/mips/isa_traits.cc: src/arch/mips/linux/process.cc: src/arch/mips/linux/process.hh: src/arch/mips/process.cc: src/arch/mips/process.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/utility.hh: 1 month of changes! src/arch/mips/isa/formats/control.isa: control formats src/arch/mips/isa/formats/mt.isa: mips mt format src/arch/mips/utility.cc: utility functions --HG-- extra : convert_revision : c1332cb5ce08b464b99fbf04f4a5cac312898784
2006-06-09 09:57:25 +02:00
panic("Copy Regs Not Implemented Yet\n");
First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined arch/mips/SConscript: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: arch/mips/process.cc: arch/mips/linux/linux.cc: arch/mips/utility.hh: arch/mips/linux/process.cc: arch/mips/int_regfile.hh: arch/mips/misc_regfile.hh: arch/mips/regfile.hh: arch/mips/types.hh: MIPS directory rearranging --HG-- rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
2006-05-08 00:50:41 +02:00
}
For now, halt context is the same as deallocating. suspend context will now take the thread off the activeThread list. src/arch/mips/isa_traits.cc: add in copy MiscRegs unimplemented function --HG-- extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
2006-07-14 19:06:37 +02:00
void
MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
panic("Copy Misc. Regs Not Implemented Yet\n");
}
First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined arch/mips/SConscript: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: arch/mips/process.cc: arch/mips/linux/linux.cc: arch/mips/utility.hh: arch/mips/linux/process.cc: arch/mips/int_regfile.hh: arch/mips/misc_regfile.hh: arch/mips/regfile.hh: arch/mips/types.hh: MIPS directory rearranging --HG-- rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
2006-05-08 00:50:41 +02:00
void
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
2006-06-06 23:32:21 +02:00
MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined arch/mips/SConscript: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: arch/mips/process.cc: arch/mips/linux/linux.cc: arch/mips/utility.hh: arch/mips/linux/process.cc: arch/mips/int_regfile.hh: arch/mips/misc_regfile.hh: arch/mips/regfile.hh: arch/mips/types.hh: MIPS directory rearranging --HG-- rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
2006-05-08 00:50:41 +02:00
{
Merging in a month of changes src/arch/isa_parser.py: Sign extend bit if you read int reg that is greater than default size src/arch/mips/SConscript: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa/base.isa: src/arch/mips/isa/bitfields.isa: src/arch/mips/isa/decoder.isa: src/arch/mips/isa/formats/basic.isa: src/arch/mips/isa/formats/branch.isa: src/arch/mips/isa/formats/formats.isa: src/arch/mips/isa/formats/fp.isa: src/arch/mips/isa/formats/int.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/noop.isa: src/arch/mips/isa/formats/tlbop.isa: src/arch/mips/isa/formats/trap.isa: src/arch/mips/isa/formats/unimp.isa: src/arch/mips/isa/formats/unknown.isa: src/arch/mips/isa/formats/util.isa: src/arch/mips/isa/includes.isa: src/arch/mips/isa/main.isa: src/arch/mips/isa/operands.isa: src/arch/mips/isa_traits.cc: src/arch/mips/linux/process.cc: src/arch/mips/linux/process.hh: src/arch/mips/process.cc: src/arch/mips/process.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/utility.hh: 1 month of changes! src/arch/mips/isa/formats/control.isa: control formats src/arch/mips/isa/formats/mt.isa: mips mt format src/arch/mips/utility.cc: utility functions --HG-- extra : convert_revision : c1332cb5ce08b464b99fbf04f4a5cac312898784
2006-06-09 09:57:25 +02:00
panic("Copy Misc. Regs Not Implemented Yet\n");
First Steps in cleaning up MIPS code - This changeset rearranges the files in the MIPS directory by moving where constants/types/classes are defined arch/mips/SConscript: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: arch/mips/process.cc: arch/mips/linux/linux.cc: arch/mips/utility.hh: arch/mips/linux/process.cc: arch/mips/int_regfile.hh: arch/mips/misc_regfile.hh: arch/mips/regfile.hh: arch/mips/types.hh: MIPS directory rearranging --HG-- rename : arch/mips/mips_linux.cc => arch/mips/linux/linux.cc rename : arch/mips/mips_linux.hh => arch/mips/linux/linux.hh rename : arch/mips/linux_process.cc => arch/mips/linux/process.cc rename : arch/mips/linux_process.hh => arch/mips/linux/process.hh extra : convert_revision : 138eee48c8ed75efcf38572f335a556aaec38fc7
2006-05-08 00:50:41 +02:00
}
Enable register windows. arch/alpha/isa_traits.hh: arch/mips/isa_traits.cc: Turned the integer register file into a class instead of a typedef to an array. arch/alpha/regfile.hh: Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. arch/mips/isa_traits.hh: Turned the integer register file into a class instead of a typedef to an array. Also moved a "using namespace" into the namespace definition. arch/sparc/isa_traits.hh: Turned the integer register file into a class instead of a typedef to an array. Also "fixed" the max number of src and dest regs. They may need to be even larger. arch/sparc/regfile.hh: Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. Created setCWP and setAltGlobals functions for the IntRegFile. cpu/cpu_exec_context.hh: Used the accessor functions for the register file, and added a changeRegFileContext function to call back into the RegFile. Used the RegFile clear function rather than memsetting it to 0. cpu/exec_context.hh: Added the changeRegFileContext function. cpu/exetrace.cc: Use the TheISA::NumIntRegs constant, and use readReg now that the integer register file is a class instead of an array. cpu/exetrace.hh: Get the address of the regs object, now that it isn't an array. --HG-- extra : convert_revision : ea2dd81be1c2e66b3c684af319eb58f8a77fd49c
2006-04-06 20:47:03 +02:00
void
IntRegFile::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(regs, NumIntRegs);
}
void
IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(regs, NumIntRegs);
}
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
void
Renaming alpha files and changing some MIPS stuff to be more like Alpha version SConscript: changed the alpha_memory.hh to memory.hh in SConscript arch/isa_parser.py: temporarily comment out o3 model arch/mips/isa/base.isa: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: Fix Up Base Class to mirror how Alpha generates StaticInsts arch/mips/faults.cc: MIPS fault.cc file arch/mips/faults.hh: MIPS fault.hh file --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-22 04:02:05 +01:00
RegFile::serialize(std::ostream &os)
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
{
Enable register windows. arch/alpha/isa_traits.hh: arch/mips/isa_traits.cc: Turned the integer register file into a class instead of a typedef to an array. arch/alpha/regfile.hh: Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. arch/mips/isa_traits.hh: Turned the integer register file into a class instead of a typedef to an array. Also moved a "using namespace" into the namespace definition. arch/sparc/isa_traits.hh: Turned the integer register file into a class instead of a typedef to an array. Also "fixed" the max number of src and dest regs. They may need to be even larger. arch/sparc/regfile.hh: Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. Created setCWP and setAltGlobals functions for the IntRegFile. cpu/cpu_exec_context.hh: Used the accessor functions for the register file, and added a changeRegFileContext function to call back into the RegFile. Used the RegFile clear function rather than memsetting it to 0. cpu/exec_context.hh: Added the changeRegFileContext function. cpu/exetrace.cc: Use the TheISA::NumIntRegs constant, and use readReg now that the integer register file is a class instead of an array. cpu/exetrace.hh: Get the address of the regs object, now that it isn't an array. --HG-- extra : convert_revision : ea2dd81be1c2e66b3c684af319eb58f8a77fd49c
2006-04-06 20:47:03 +02:00
intRegFile.serialize(os);
infinitesimal small baby steps toward MIPS actually working arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-15 22:26:40 +01:00
//SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
2006-03-08 08:05:38 +01:00
//SERIALIZE_SCALAR(miscRegs.fpcr);
//SERIALIZE_SCALAR(miscRegs.uniq);
//SERIALIZE_SCALAR(miscRegs.lock_flag);
//SERIALIZE_SCALAR(miscRegs.lock_addr);
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
2006-03-08 08:05:38 +01:00
SERIALIZE_SCALAR(nnpc);
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
}
void
Renaming alpha files and changing some MIPS stuff to be more like Alpha version SConscript: changed the alpha_memory.hh to memory.hh in SConscript arch/isa_parser.py: temporarily comment out o3 model arch/mips/isa/base.isa: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: Fix Up Base Class to mirror how Alpha generates StaticInsts arch/mips/faults.cc: MIPS fault.cc file arch/mips/faults.hh: MIPS fault.hh file --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-22 04:02:05 +01:00
RegFile::unserialize(Checkpoint *cp, const std::string &section)
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
{
Enable register windows. arch/alpha/isa_traits.hh: arch/mips/isa_traits.cc: Turned the integer register file into a class instead of a typedef to an array. arch/alpha/regfile.hh: Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. arch/mips/isa_traits.hh: Turned the integer register file into a class instead of a typedef to an array. Also moved a "using namespace" into the namespace definition. arch/sparc/isa_traits.hh: Turned the integer register file into a class instead of a typedef to an array. Also "fixed" the max number of src and dest regs. They may need to be even larger. arch/sparc/regfile.hh: Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. Created setCWP and setAltGlobals functions for the IntRegFile. cpu/cpu_exec_context.hh: Used the accessor functions for the register file, and added a changeRegFileContext function to call back into the RegFile. Used the RegFile clear function rather than memsetting it to 0. cpu/exec_context.hh: Added the changeRegFileContext function. cpu/exetrace.cc: Use the TheISA::NumIntRegs constant, and use readReg now that the integer register file is a class instead of an array. cpu/exetrace.hh: Get the address of the regs object, now that it isn't an array. --HG-- extra : convert_revision : ea2dd81be1c2e66b3c684af319eb58f8a77fd49c
2006-04-06 20:47:03 +02:00
intRegFile.unserialize(cp, section);
infinitesimal small baby steps toward MIPS actually working arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-15 22:26:40 +01:00
//UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
2006-03-08 08:05:38 +01:00
//UNSERIALIZE_SCALAR(miscRegs.fpcr);
//UNSERIALIZE_SCALAR(miscRegs.uniq);
//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
Some stuff aparently didn't get committed which was from before the new repository was created. SConscript: There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created. arch/isa_parser.py: The isa parser now supports include directives. These are done with ##include build/SConstruct: The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type. arch/alpha/SConscript: This SConscript adds the alpha specific source arch/sparc/isa_desc/operands.h: This sets up the operand types that the sparc isa uses arch/sparc/isa_traits.cc: Implementation of sparc specific things, like a register file with windows build/build_options/default/SPARC_SE: The default options for a sparc syscall emulation build. --HG-- extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-25 01:57:17 +01:00
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.* which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
2006-03-08 08:05:38 +01:00
UNSERIALIZE_SCALAR(nnpc);
Renaming alpha files and changing some MIPS stuff to be more like Alpha version SConscript: changed the alpha_memory.hh to memory.hh in SConscript arch/isa_parser.py: temporarily comment out o3 model arch/mips/isa/base.isa: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: Fix Up Base Class to mirror how Alpha generates StaticInsts arch/mips/faults.cc: MIPS fault.cc file arch/mips/faults.hh: MIPS fault.hh file --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-22 04:02:05 +01:00
}
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