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gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

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ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
sim_seconds 0.080749 # Number of seconds simulated
sim_ticks 80748998500 # Number of ticks simulated
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
host_inst_rate 110010 # Simulator instruction rate (inst/s)
host_tick_rate 171236576 # Simulator tick rate (ticks/s)
host_mem_usage 368976 # Number of bytes of host memory used
host_seconds 471.56 # Real time elapsed on the host
sim_insts 51876948 # Number of instructions simulated
system.l2c.replacements 94981 # number of replacements
system.l2c.tagsinuse 38166.685860 # Cycle average of tags in use
system.l2c.total_refs 1060946 # Total number of references to valid blocks.
system.l2c.sampled_refs 127430 # Sample count of references to valid blocks.
system.l2c.avg_refs 8.325716 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.occ_blocks::0 6723.855274 # Average occupied blocks per context
system.l2c.occ_blocks::1 31442.830586 # Average occupied blocks per context
system.l2c.occ_percent::0 0.102598 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.479780 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0 746399 # number of ReadReq hits
system.l2c.ReadReq_hits::1 123135 # number of ReadReq hits
system.l2c.ReadReq_hits::total 869534 # number of ReadReq hits
system.l2c.Writeback_hits::0 435298 # number of Writeback hits
system.l2c.Writeback_hits::total 435298 # number of Writeback hits
system.l2c.UpgradeReq_hits::0 24 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::0 60890 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 60890 # number of ReadExReq hits
system.l2c.demand_hits::0 807289 # number of demand (read+write) hits
system.l2c.demand_hits::1 123135 # number of demand (read+write) hits
system.l2c.demand_hits::total 930424 # number of demand (read+write) hits
system.l2c.overall_hits::0 807289 # number of overall hits
system.l2c.overall_hits::1 123135 # number of overall hits
system.l2c.overall_hits::total 930424 # number of overall hits
system.l2c.ReadReq_misses::0 21130 # number of ReadReq misses
system.l2c.ReadReq_misses::1 101 # number of ReadReq misses
system.l2c.ReadReq_misses::total 21231 # number of ReadReq misses
system.l2c.UpgradeReq_misses::0 1677 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1677 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0 107756 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 107756 # number of ReadExReq misses
system.l2c.demand_misses::0 128886 # number of demand (read+write) misses
system.l2c.demand_misses::1 101 # number of demand (read+write) misses
system.l2c.demand_misses::total 128987 # number of demand (read+write) misses
system.l2c.overall_misses::0 128886 # number of overall misses
system.l2c.overall_misses::1 101 # number of overall misses
system.l2c.overall_misses::total 128987 # number of overall misses
system.l2c.ReadReq_miss_latency 1109806000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency 780500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency 5651942000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency 6761748000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency 6761748000 # number of overall miss cycles
system.l2c.ReadReq_accesses::0 767529 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 123236 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 890765 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0 435298 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 435298 # number of Writeback accesses(hits+misses)
Stats: Update stats for the previous change.
2011-08-08 00:41:09 +02:00
system.l2c.UpgradeReq_accesses::0 1701 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1701 # number of UpgradeReq accesses(hits+misses)
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.ReadExReq_accesses::0 168646 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 168646 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0 936175 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 123236 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1059411 # number of demand (read+write) accesses
system.l2c.overall_accesses::0 936175 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 123236 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1059411 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0 0.027530 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.000820 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.028349 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0 0.985891 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0 0.638948 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0 0.137673 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.000820 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.138493 # miss rate for demand accesses
system.l2c.overall_miss_rate::0 0.137673 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.000820 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.138493 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0 52522.763843 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 10988178.217822 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 11040700.981665 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0 465.414431 # average UpgradeReq miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.ReadExReq_avg_miss_latency::0 52451.297376 # average ReadExReq miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.demand_avg_miss_latency::0 52463.013826 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 66948000 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 67000463.013826 # average overall miss latency
system.l2c.overall_avg_miss_latency::0 52463.013826 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 66948000 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 67000463.013826 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.writebacks 87796 # number of writebacks
Stats: Update stats for the previous change.
2011-08-08 00:41:09 +02:00
system.l2c.ReadReq_mshr_hits 58 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits 58 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits 58 # number of overall MSHR hits
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.ReadReq_mshr_misses 21173 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses 1677 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses 107756 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses 128929 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses 128929 # number of overall MSHR misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.ReadReq_mshr_miss_latency 848032500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency 67081500 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency 4311568500 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency 5159601000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency 5159601000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency 28946618000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency 748818447 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency 29695436447 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.027586 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 0.171809 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.199394 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0 0.985891 # mshr miss rate for UpgradeReq accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.ReadExReq_mshr_miss_rate::0 0.638948 # mshr miss rate for ReadExReq accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.l2c.demand_mshr_miss_rate::0 0.137719 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 1.046196 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 1.183915 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0 0.137719 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 1.046196 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 1.183915 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40052.543333 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.894454 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40012.328780 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dtb.read_hits 28177040 # DTB read hits
system.cpu.dtb.read_misses 72386 # DTB read misses
system.cpu.dtb.write_hits 7691310 # DTB write hits
system.cpu.dtb.write_misses 13556 # DTB write misses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
O3/ARM: Update stats for recent changes.
2011-05-05 03:38:27 +02:00
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dtb.flush_entries 2922 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 4054 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 1092 # Number of TLB faults due to prefetch
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dtb.perms_faults 940 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 28249426 # DTB read accesses
system.cpu.dtb.write_accesses 7704866 # DTB write accesses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dtb.hits 35868350 # DTB hits
system.cpu.dtb.misses 85942 # DTB misses
system.cpu.dtb.accesses 35954292 # DTB accesses
system.cpu.itb.inst_hits 7355634 # ITB inst hits
system.cpu.itb.inst_misses 7654 # ITB inst misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.itb.flush_entries 1641 # Number of entries that have been flushed from TLB
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.itb.perms_faults 4616 # Number of TLB faults due to permissions restrictions
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.itb.inst_accesses 7363288 # ITB inst accesses
system.cpu.itb.hits 7355634 # DTB hits
system.cpu.itb.misses 7654 # DTB misses
system.cpu.itb.accesses 7363288 # DTB accesses
system.cpu.numCycles 161497998 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.BPredUnit.lookups 13590326 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11456360 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 648707 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 12127952 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 9362916 # Number of BTB hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.BPredUnit.usedRAS 895596 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 148738 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 16866017 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 67484906 # Number of instructions fetch has processed
system.cpu.fetch.Branches 13590326 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 10258512 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 17034266 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4123173 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 93207 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 55393473 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 18245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 90602 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 7350509 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 337942 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 4453 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 92525962 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.899758 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.157294 # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.fetch.rateDist::0 75510639 81.61% 81.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1420262 1.53% 83.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1864587 2.02% 85.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1402898 1.52% 86.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4892259 5.29% 91.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 936046 1.01% 92.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 818442 0.88% 93.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 713663 0.77% 94.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4967166 5.37% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.fetch.rateDist::total 92525962 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.084152 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.417868 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 18966191 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 54065669 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 15364429 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1171991 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2957682 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 1326698 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 73964 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 80385244 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 241077 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2957682 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 20606631 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 33478689 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 16542065 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 13879452 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5061443 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 77021348 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 458130 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 143873 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2652425 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 147 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 79088993 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 335825078 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 335758422 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 66656 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 51887194 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27201798 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 847863 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 665654 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 14013888 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 13554810 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 9178167 # Number of stores inserted to the mem dependence unit.
Stats: Update stats for the previous change.
2011-08-08 00:41:09 +02:00
system.cpu.memDep0.conflictingLoads 336 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 727 # Number of conflicting stores.
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iq.iqInstsAdded 69117949 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4041398 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 82091279 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 240337 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 20597655 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 41996969 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1078579 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 92525962 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.887224 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.470662 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iq.issued_per_cycle::0 58116859 62.81% 62.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14058568 15.19% 78.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 6650411 7.19% 85.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 4537690 4.90% 90.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6374184 6.89% 96.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1626800 1.76% 98.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 758213 0.82% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 287091 0.31% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 116146 0.13% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iq.issued_per_cycle::total 92525962 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iq.fu_full::IntAlu 27856 0.57% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 1 0.00% 0.57% # attempts to use FU when none available
Stats: Update stats for the previous change.
2011-08-08 00:41:09 +02:00
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.57% # attempts to use FU when none available
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iq.fu_full::MemRead 4535089 92.61% 93.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 334124 6.82% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::No_OpClass 2393223 2.92% 2.92% # Type of FU issued
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iq.FU_type_0::IntAlu 42162127 51.36% 54.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 71788 0.09% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 29248881 35.63% 89.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 8214337 10.01% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iq.FU_type_0::total 82091279 # Type of FU issued
system.cpu.iq.rate 0.508311 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4897070 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.059654 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 261914662 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 94097771 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 62682872 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 16678 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9625 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6496 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 84586375 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 8751 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 425783 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 4375336 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13490 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 405193 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2100755 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 17024856 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 9533 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iew.iewSquashCycles 2957682 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 21379595 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 254604 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 73328942 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 354348 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 13554810 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 9178167 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 4009809 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13226 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 41705 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 405193 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 534373 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 174123 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 708496 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 80713996 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28682342 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1377283 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iew.exec_nop 169595 # number of nop insts executed
system.cpu.iew.exec_refs 36687563 # number of memory reference insts executed
system.cpu.iew.exec_branches 10549834 # Number of branches executed
system.cpu.iew.exec_stores 8005221 # Number of stores executed
system.cpu.iew.exec_rate 0.499783 # Inst execution rate
system.cpu.iew.wb_sent 80082379 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 62689368 # cumulative count of insts written-back
system.cpu.iew.wb_producers 33196620 # num instructions producing a value
system.cpu.iew.wb_consumers 59589146 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.iew.wb_rate 0.388174 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.557092 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.commit.commitCommittedInsts 52000178 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 19092846 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2962819 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 623054 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 89568308 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.580564 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.463287 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.commit.committed_per_cycle::0 69902534 78.04% 78.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 9240090 10.32% 88.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 2668754 2.98% 91.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 1387483 1.55% 92.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3444879 3.85% 96.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 818955 0.91% 97.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 553093 0.62% 98.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 352878 0.39% 98.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1199642 1.34% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.commit.committed_per_cycle::total 89568308 # Number of insts commited each cycle
system.cpu.commit.count 52000178 # Number of instructions committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.commit.refs 16256886 # Number of memory references committed
system.cpu.commit.loads 9179474 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 3 # Number of memory barriers committed
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.commit.branches 8429121 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions.
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.commit.int_insts 42423758 # Number of committed integer instructions.
system.cpu.commit.function_calls 530189 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1199642 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.rob.rob_reads 158520597 # The number of ROB reads
system.cpu.rob.rob_writes 145188457 # The number of ROB writes
system.cpu.timesIdled 1073623 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 68972036 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 51876948 # Number of Instructions Simulated
system.cpu.committedInsts_total 51876948 # Number of Instructions Simulated
system.cpu.cpi 3.113098 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.113098 # CPI: Total CPI of All Threads
system.cpu.ipc 0.321223 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.321223 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 356113054 # number of integer regfile reads
system.cpu.int_regfile_writes 64703490 # number of integer regfile writes
system.cpu.fp_regfile_reads 5644 # number of floating regfile reads
system.cpu.fp_regfile_writes 1932 # number of floating regfile writes
system.cpu.misc_regfile_reads 88421211 # number of misc regfile reads
system.cpu.misc_regfile_writes 512467 # number of misc regfile writes
system.cpu.icache.replacements 513097 # number of replacements
system.cpu.icache.tagsinuse 496.956364 # Cycle average of tags in use
system.cpu.icache.total_refs 6781343 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 513609 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13.203318 # Average number of references to valid blocks.
Stats: Update stats for the previous change.
2011-08-08 00:41:09 +02:00
system.cpu.icache.warmup_cycle 5987250000 # Cycle when the warmup percentage was hit.
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.occ_blocks::0 496.956364 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.970618 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0 6781343 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6781343 # number of ReadReq hits
system.cpu.icache.demand_hits::0 6781343 # number of demand (read+write) hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.demand_hits::total 6781343 # number of demand (read+write) hits
system.cpu.icache.overall_hits::0 6781343 # number of overall hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.overall_hits::1 0 # number of overall hits
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.overall_hits::total 6781343 # number of overall hits
system.cpu.icache.ReadReq_misses::0 569051 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 569051 # number of ReadReq misses
system.cpu.icache.demand_misses::0 569051 # number of demand (read+write) misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.demand_misses::total 569051 # number of demand (read+write) misses
system.cpu.icache.overall_misses::0 569051 # number of overall misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.overall_misses::1 0 # number of overall misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.overall_misses::total 569051 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 8379802495 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 8379802495 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 8379802495 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0 7350394 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 7350394 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0 7350394 # number of demand (read+write) accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.demand_accesses::total 7350394 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0 7350394 # number of overall (read+write) accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.overall_accesses::total 7350394 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0 0.077418 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0 0.077418 # miss rate for demand accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.overall_miss_rate::0 0.077418 # miss rate for overall accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::0 14725.925260 # average ReadReq miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.demand_avg_miss_latency::0 14725.925260 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.overall_avg_miss_latency::0 14725.925260 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 1742497 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 7813.887892 # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.writebacks 42974 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 55439 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 55439 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 55439 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 513612 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 513612 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 513612 # number of overall MSHR misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency 6212945497 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 6212945497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 6212945497 # number of overall MSHR miss cycles
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency 5831500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency 5831500 # number of overall MSHR uncacheable cycles
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.069875 # mshr miss rate for ReadReq accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.demand_mshr_miss_rate::0 0.069875 # mshr miss rate for demand accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.overall_mshr_miss_rate::0 0.069875 # mshr miss rate for overall accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12096.573867 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12096.573867 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12096.573867 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.replacements 424539 # number of replacements
system.cpu.dcache.tagsinuse 511.742336 # Cycle average of tags in use
system.cpu.dcache.total_refs 14092021 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 425051 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 33.153718 # Average number of references to valid blocks.
Stats: Update stats for the previous change.
2011-08-08 00:41:09 +02:00
system.cpu.dcache.warmup_cycle 48622000 # Cycle when the warmup percentage was hit.
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.occ_blocks::0 511.742336 # Average occupied blocks per context
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.ReadReq_hits::0 9263117 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 9263117 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0 4618459 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4618459 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::0 103676 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 103676 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::0 104941 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 104941 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::0 13881576 # number of demand (read+write) hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.demand_hits::total 13881576 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0 13881576 # number of overall hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.overall_hits::1 0 # number of overall hits
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.overall_hits::total 13881576 # number of overall hits
system.cpu.dcache.ReadReq_misses::0 533393 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 533393 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0 2044461 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2044461 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::0 6632 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 6632 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::0 2577854 # number of demand (read+write) misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.demand_misses::total 2577854 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0 2577854 # number of overall misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.overall_misses::1 0 # number of overall misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.overall_misses::total 2577854 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 7849628500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 81637522770 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 99339500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 89487151270 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 89487151270 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0 9796510 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9796510 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0 6662920 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6662920 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::0 110308 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 110308 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::0 104941 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 104941 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0 16459430 # number of demand (read+write) accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.demand_accesses::total 16459430 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0 16459430 # number of overall (read+write) accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.overall_accesses::total 16459430 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0 0.054447 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0 0.306842 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060123 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::0 0.156619 # miss rate for demand accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.overall_miss_rate::0 0.156619 # miss rate for overall accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::0 14716.407039 # average ReadReq miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.WriteReq_avg_miss_latency::0 39931.073652 # average WriteReq miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14978.814837 # average LoadLockedReq miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.demand_avg_miss_latency::0 34713.816713 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.overall_avg_miss_latency::0 34713.816713 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 9881489 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 841000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1354 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.997784 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.writebacks 392324 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 282537 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1874151 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 1046 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 2156688 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 2156688 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 250856 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 170310 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses 5586 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses 421166 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 421166 # number of overall MSHR misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency 3355794000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 6558107489 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66303500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 9913901489 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 9913901489 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199628000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 946945664 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 39146573664 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025607 # mshr miss rate for ReadReq accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025561 # mshr miss rate for WriteReq accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050640 # mshr miss rate for LoadLockedReq accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.demand_mshr_miss_rate::0 0.025588 # mshr miss rate for demand accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.overall_mshr_miss_rate::0 0.025588 # mshr miss rate for overall accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 12:37:45 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13377.371879 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38506.884440 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11869.584676 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.avg_refs no_value # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.overall_misses::0 0 # number of overall misses
system.iocache.overall_misses::1 0 # number of overall misses
system.iocache.overall_misses::total 0 # number of overall misses
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks 0 # number of writebacks
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink