2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-05-16 01:25:35 +02:00
|
|
|
global.BPredUnit.BTBHits 236329759 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups
|
|
|
|
|
global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 265702680 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target.
|
|
|
|
|
host_inst_rate 104740 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 154596 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 16574.74 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 38540500 # Simulator tick rate (ticks/s)
|
|
|
|
|
memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores.
|
|
|
|
|
memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit.
|
2006-10-12 21:04:14 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2006-12-05 01:07:00 +01:00
|
|
|
sim_insts 1736043781 # Number of instructions simulated
|
2007-05-16 01:25:35 +02:00
|
|
|
sim_seconds 0.638799 # Number of seconds simulated
|
|
|
|
|
sim_ticks 638798750000 # Number of ticks simulated
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:branches 214632552 # Number of branches committed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 1240430038
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-05-16 01:25:35 +02:00
|
|
|
0 616961832 4973.77%
|
|
|
|
|
1 236071207 1903.14%
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|
|
|
|
2 130159070 1049.31%
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|
|
|
|
3 77572840 625.37%
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|
|
|
|
4 40072787 323.06%
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|
|
|
|
5 42334502 341.29%
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|
|
|
|
6 22413470 180.69%
|
|
|
|
|
7 14526859 117.11%
|
|
|
|
|
8 60317471 486.26%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 445666361 # Number of loads committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_hits 609102856 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 11929003 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.replacements 9171759 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 2245633 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 1277597526
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-05-16 01:25:35 +02:00
|
|
|
0 882806946 6909.90%
|
|
|
|
|
1 27356477 214.12%
|
|
|
|
|
2 16416749 128.50%
|
|
|
|
|
3 27123610 212.30%
|
|
|
|
|
4 80197027 627.72%
|
|
|
|
|
5 46838848 366.62%
|
|
|
|
|
6 25144427 196.81%
|
|
|
|
|
7 24073126 188.42%
|
|
|
|
|
8 147640316 1155.61%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_misses 947 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_hits 277956896 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_misses 947 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.replacements 1 # number of replacements
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 231142223 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 168419462 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.WB:producers 991749121 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2006-12-05 01:07:00 +01:00
|
|
|
(null) 0 0.00% # Type of FU issued
|
2007-05-16 01:25:35 +02:00
|
|
|
IntAlu 1224165146 65.09% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
IntMult 78 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2007-05-16 01:25:35 +02:00
|
|
|
FloatAdd 199 0.00% # Type of FU issued
|
2006-12-05 01:07:00 +01:00
|
|
|
FloatCmp 15 0.00% # Type of FU issued
|
2007-05-16 01:25:35 +02:00
|
|
|
FloatCvt 141 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 13 0.00% # Type of FU issued
|
2006-12-05 01:07:00 +01:00
|
|
|
FloatDiv 24 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-05-16 01:25:35 +02:00
|
|
|
MemRead 487297898 25.91% # Type of FU issued
|
|
|
|
|
MemWrite 169129941 8.99% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst)
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2007-05-16 01:25:35 +02:00
|
|
|
IntAlu 753308 5.08% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-05-16 01:25:35 +02:00
|
|
|
MemRead 10126775 68.23% # attempts to use FU when none available
|
|
|
|
|
MemWrite 3961138 26.69% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-05-16 01:25:35 +02:00
|
|
|
0 550473495 4308.66%
|
|
|
|
|
1 242915598 1901.35%
|
|
|
|
|
2 174612702 1366.73%
|
|
|
|
|
3 111937959 876.16%
|
|
|
|
|
4 91216702 713.97%
|
|
|
|
|
5 63235343 494.96%
|
|
|
|
|
6 32411117 253.69%
|
|
|
|
|
7 9228529 72.23%
|
|
|
|
|
8 1566081 12.26%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_hits 9224685 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 2197691 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.replacements 2135792 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 1039396 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 1277597526 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
