2006-10-12 21:04:14 +02:00
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---------- Begin Simulation Statistics ----------
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2011-02-08 04:23:13 +01:00
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host_inst_rate 1382202 # Simulator instruction rate (inst/s)
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host_mem_usage 224632 # Number of bytes of host memory used
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host_seconds 288.43 # Real time elapsed on the host
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host_tick_rate 691100750 # Simulator tick rate (ticks/s)
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2006-10-12 21:04:14 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2007-08-27 05:27:53 +02:00
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sim_insts 398664595 # Number of instructions simulated
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2007-04-27 20:35:58 +02:00
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sim_seconds 0.199332 # Number of seconds simulated
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2007-08-27 05:27:53 +02:00
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sim_ticks 199332411500 # Number of ticks simulated
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.data_accesses 168275274 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 168275218 # DTB hits
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system.cpu.dtb.data_misses 56 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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2007-08-27 05:27:53 +02:00
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system.cpu.dtb.read_accesses 94754510 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 94754489 # DTB read hits
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system.cpu.dtb.read_misses 21 # DTB read misses
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system.cpu.dtb.write_accesses 73520764 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 73520729 # DTB write hits
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system.cpu.dtb.write_misses 35 # DTB write misses
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2006-12-05 01:07:00 +01:00
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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2009-04-09 07:21:30 +02:00
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.fetch_accesses 398664824 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_hits 398664651 # ITB hits
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system.cpu.itb.fetch_misses 173 # ITB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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2006-12-05 01:07:00 +01:00
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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2007-08-27 05:27:53 +02:00
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system.cpu.numCycles 398664824 # number of cpu cycles simulated
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2011-02-08 04:23:13 +01:00
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.num_busy_cycles 398664824 # Number of busy cycles
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system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
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system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
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system.cpu.num_fp_insts 155295119 # number of float instructions
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system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
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system.cpu.num_func_calls 16015498 # number of times a function call or return occured
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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2007-08-27 05:27:53 +02:00
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system.cpu.num_insts 398664595 # Number of instructions executed
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2011-02-08 04:23:13 +01:00
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system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
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system.cpu.num_int_insts 316365907 # number of integer instructions
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system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
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system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
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system.cpu.num_load_insts 94754510 # Number of load instructions
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system.cpu.num_mem_refs 168275274 # number of memory refs
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system.cpu.num_store_insts 73520764 # Number of store instructions
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2006-12-05 01:07:00 +01:00
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system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
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2006-10-12 21:04:14 +02:00
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---------- End Simulation Statistics ----------
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