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gem5/src/arch/x86/isa.cc

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Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-07-09 08:02:20 +02:00
/*
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
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#include "arch/x86/isa.hh"
style: [patch 1/22] use /r/3648/ to reorganize includes
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#include "arch/x86/decoder.hh"
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#include "arch/x86/tlb.hh"
#include "cpu/base.hh"
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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#include "cpu/thread_context.hh"
arch: Make the ISA class inherit from SimObject The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
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#include "params/X86ISA.hh"
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#include "sim/serialize.hh"
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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namespace X86ISA
{
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void
ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
X86: Move address based decode caching in front of the predecoder. The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
ThreadContext *tc)
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{
build: fix compile problems pointed out by gcc 4.4
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HandyM5Reg m5reg = 0;
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if (efer.lma) {
m5reg.mode = LongMode;
if (csAttr.longMode)
m5reg.submode = SixtyFourBitMode;
else
m5reg.submode = CompatabilityMode;
} else {
m5reg.mode = LegacyMode;
if (cr0.pe) {
if (rflags.vm)
m5reg.submode = Virtual8086Mode;
else
m5reg.submode = ProtectedMode;
} else {
m5reg.submode = RealMode;
}
}
m5reg.cpl = csAttr.dpl;
m5reg.paging = cr0.pg;
m5reg.prot = cr0.pe;
// Compute the default and alternate operand size.
if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
m5reg.defOp = 2;
m5reg.altOp = 1;
} else {
m5reg.defOp = 1;
m5reg.altOp = 2;
}
// Compute the default and alternate address size.
if (m5reg.submode == SixtyFourBitMode) {
m5reg.defAddr = 3;
m5reg.altAddr = 2;
} else if (csAttr.defaultSize) {
m5reg.defAddr = 2;
m5reg.altAddr = 1;
} else {
m5reg.defAddr = 1;
m5reg.altAddr = 2;
}
// Compute the stack size
if (m5reg.submode == SixtyFourBitMode) {
m5reg.stack = 3;
} else if (ssAttr.defaultSize) {
m5reg.stack = 2;
} else {
m5reg.stack = 1;
}
regVal[MISCREG_M5_REG] = m5reg;
X86: Move address based decode caching in front of the predecoder. The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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if (tc)
tc->getDecoderPtr()->setM5Reg(m5reg);
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}
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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void
ISA::clear()
{
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// Blank everything. 0 might not be an appropriate value for some things,
// but it is for most.
memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
regVal[MISCREG_DR7] = 1 << 10;
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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}
arch: Make the ISA class inherit from SimObject The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
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ISA::ISA(Params *p)
: SimObject(p)
{
clear();
}
const X86ISAParams *
ISA::params() const
{
return dynamic_cast<const Params *>(_params);
}
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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MiscReg
arch: Make readMiscRegNoEffect const throughout Finally took the plunge and made this apply to all ISAs, not just ARM.
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ISA::readMiscRegNoEffect(int miscReg) const
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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{
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// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to read them directly.
x86: create function to check miscreg validity In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others.
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assert(isValidMiscReg(miscReg));
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return regVal[miscReg];
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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}
MiscReg
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ISA::readMiscReg(int miscReg, ThreadContext * tc)
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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{
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if (miscReg == MISCREG_TSC) {
return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
}
x86: implement x87 fp instruction fnstsw This patch implements the fnstsw instruction. The code was originally written by Vince Weaver. Gabe had made some comments about the code, but those were never addressed. This patch addresses those comments.
2012-12-30 19:45:50 +01:00
if (miscReg == MISCREG_FSW) {
MiscReg fsw = regVal[MISCREG_FSW];
MiscReg top = regVal[MISCREG_X87_TOP];
return (fsw & (~(7ULL << 11))) + (top << 11);
}
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return readMiscRegNoEffect(miscReg);
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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}
void
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ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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{
X86: Fold the MiscRegFile all the way into the ISA object.
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// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to write to them directly.
x86: create function to check miscreg validity In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others.
2016-02-07 02:21:20 +01:00
assert(isValidMiscReg(miscReg));
x86: Adjust the size of the values written to the x87 misc registers All x87 misc registers are implemented in an array of 64 bit values but in real hardware the size of some of these registers is smaller. Previsouly all 64 bits where incorrectly set and then later read. To ensure correctness we mask the value in setMiscRegNoEffect to write only the valid bits. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-07-04 17:43:47 +02:00
HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
switch (miscReg) {
case MISCREG_FSW:
val &= (1ULL << 16) - 1;
regVal[miscReg] = val;
miscReg = MISCREG_X87_TOP;
val <<= 11;
case MISCREG_X87_TOP:
val &= (1ULL << 3) - 1;
break;
case MISCREG_FTW:
val &= (1ULL << 8) - 1;
break;
case MISCREG_FCW:
case MISCREG_FOP:
val &= (1ULL << 16) - 1;
break;
case MISCREG_MXCSR:
val &= (1ULL << 32) - 1;
break;
case MISCREG_FISEG:
case MISCREG_FOSEG:
if (m5Reg.submode != SixtyFourBitMode)
val &= (1ULL << 16) - 1;
break;
case MISCREG_FIOFF:
case MISCREG_FOOFF:
if (m5Reg.submode != SixtyFourBitMode)
val &= (1ULL << 32) - 1;
break;
default:
break;
}
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regVal[miscReg] = val;
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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}
void
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ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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{
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MiscReg newVal = val;
switch(miscReg)
{
case MISCREG_CR0:
{
CR0 toggled = regVal[miscReg] ^ val;
CR0 newCR0 = val;
Efer efer = regVal[MISCREG_EFER];
if (toggled.pg && efer.lme) {
if (newCR0.pg) {
//Turning on long mode
efer.lma = 1;
regVal[MISCREG_EFER] = efer;
} else {
//Turning off long mode
efer.lma = 0;
regVal[MISCREG_EFER] = efer;
}
}
if (toggled.pg) {
arch: Add support for invalidating TLBs when draining This patch adds support for the memInvalidate() drain method. TLB flushing is requested by calling the virtual flushAll() method on the TLB. Note: This patch renames invalidateAll() to flushAll() on x86 and SPARC to make the interface consistent across all supported architectures.
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tc->getITBPtr()->flushAll();
tc->getDTBPtr()->flushAll();
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}
//This must always be 1.
newCR0.et = 1;
newVal = newCR0;
updateHandyM5Reg(regVal[MISCREG_EFER],
newCR0,
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
X86: Move address based decode caching in front of the predecoder. The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-05 02:00:44 +01:00
regVal[MISCREG_RFLAGS],
tc);
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}
break;
case MISCREG_CR2:
break;
case MISCREG_CR3:
arch: Add support for invalidating TLBs when draining This patch adds support for the memInvalidate() drain method. TLB flushing is requested by calling the virtual flushAll() method on the TLB. Note: This patch renames invalidateAll() to flushAll() on x86 and SPARC to make the interface consistent across all supported architectures.
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tc->getITBPtr()->flushNonGlobal();
tc->getDTBPtr()->flushNonGlobal();
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break;
case MISCREG_CR4:
{
CR4 toggled = regVal[miscReg] ^ val;
if (toggled.pae || toggled.pse || toggled.pge) {
arch: Add support for invalidating TLBs when draining This patch adds support for the memInvalidate() drain method. TLB flushing is requested by calling the virtual flushAll() method on the TLB. Note: This patch renames invalidateAll() to flushAll() on x86 and SPARC to make the interface consistent across all supported architectures.
2013-01-07 19:05:40 +01:00
tc->getITBPtr()->flushAll();
tc->getDTBPtr()->flushAll();
X86: Fold the MiscRegFile all the way into the ISA object.
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}
}
break;
case MISCREG_CR8:
break;
case MISCREG_CS_ATTR:
{
SegAttr toggled = regVal[miscReg] ^ val;
SegAttr newCSAttr = val;
if (toggled.longMode) {
if (newCSAttr.longMode) {
regVal[MISCREG_ES_EFF_BASE] = 0;
regVal[MISCREG_CS_EFF_BASE] = 0;
regVal[MISCREG_SS_EFF_BASE] = 0;
regVal[MISCREG_DS_EFF_BASE] = 0;
} else {
regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
}
}
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
newCSAttr,
regVal[MISCREG_SS_ATTR],
X86: Move address based decode caching in front of the predecoder. The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-05 02:00:44 +01:00
regVal[MISCREG_RFLAGS],
tc);
X86: Fold the MiscRegFile all the way into the ISA object.
2009-07-10 05:29:02 +02:00
}
break;
case MISCREG_SS_ATTR:
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
val,
X86: Move address based decode caching in front of the predecoder. The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-05 02:00:44 +01:00
regVal[MISCREG_RFLAGS],
tc);
X86: Fold the MiscRegFile all the way into the ISA object.
2009-07-10 05:29:02 +02:00
break;
// These segments always actually use their bases, or in other words
// their effective bases must stay equal to their actual bases.
case MISCREG_FS_BASE:
case MISCREG_GS_BASE:
case MISCREG_HS_BASE:
case MISCREG_TSL_BASE:
case MISCREG_TSG_BASE:
case MISCREG_TR_BASE:
case MISCREG_IDTR_BASE:
regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
break;
// These segments ignore their bases in 64 bit mode.
// their effective bases must stay equal to their actual bases.
case MISCREG_ES_BASE:
case MISCREG_CS_BASE:
case MISCREG_SS_BASE:
case MISCREG_DS_BASE:
{
Efer efer = regVal[MISCREG_EFER];
SegAttr csAttr = regVal[MISCREG_CS_ATTR];
if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
regVal[MISCREG_SEG_EFF_BASE(miscReg -
MISCREG_SEG_BASE_BASE)] = val;
}
break;
case MISCREG_TSC:
regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
return;
case MISCREG_DR0:
case MISCREG_DR1:
case MISCREG_DR2:
case MISCREG_DR3:
/* These should eventually set up breakpoints. */
break;
case MISCREG_DR4:
miscReg = MISCREG_DR6;
/* Fall through to have the same effects as DR6. */
case MISCREG_DR6:
{
DR6 dr6 = regVal[MISCREG_DR6];
DR6 newDR6 = val;
dr6.b0 = newDR6.b0;
dr6.b1 = newDR6.b1;
dr6.b2 = newDR6.b2;
dr6.b3 = newDR6.b3;
dr6.bd = newDR6.bd;
dr6.bs = newDR6.bs;
dr6.bt = newDR6.bt;
newVal = dr6;
}
break;
case MISCREG_DR5:
miscReg = MISCREG_DR7;
/* Fall through to have the same effects as DR7. */
case MISCREG_DR7:
{
DR7 dr7 = regVal[MISCREG_DR7];
DR7 newDR7 = val;
dr7.l0 = newDR7.l0;
dr7.g0 = newDR7.g0;
if (dr7.l0 || dr7.g0) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 0. */
}
dr7.l1 = newDR7.l1;
dr7.g1 = newDR7.g1;
if (dr7.l1 || dr7.g1) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 1. */
}
dr7.l2 = newDR7.l2;
dr7.g2 = newDR7.g2;
if (dr7.l2 || dr7.g2) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 2. */
}
dr7.l3 = newDR7.l3;
dr7.g3 = newDR7.g3;
if (dr7.l3 || dr7.g3) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 3. */
}
dr7.gd = newDR7.gd;
dr7.rw0 = newDR7.rw0;
dr7.len0 = newDR7.len0;
dr7.rw1 = newDR7.rw1;
dr7.len1 = newDR7.len1;
dr7.rw2 = newDR7.rw2;
dr7.len2 = newDR7.len2;
dr7.rw3 = newDR7.rw3;
dr7.len3 = newDR7.len3;
}
break;
case MISCREG_M5_REG:
// Writing anything to the m5reg with side effects makes it update
// based on the current values of the relevant registers. The actual
// value written is discarded.
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
X86: Move address based decode caching in front of the predecoder. The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-05 02:00:44 +01:00
regVal[MISCREG_RFLAGS],
tc);
X86: Fold the MiscRegFile all the way into the ISA object.
2009-07-10 05:29:02 +02:00
return;
default:
break;
}
setMiscRegNoEffect(miscReg, newVal);
}
void
sim: Refactor the serialization base class Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code.
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ISA::serialize(CheckpointOut &cp) const
X86: Fold the MiscRegFile all the way into the ISA object.
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{
SERIALIZE_ARRAY(regVal, NumMiscRegs);
}
void
sim: Refactor the serialization base class Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code.
2015-07-07 10:51:03 +02:00
ISA::unserialize(CheckpointIn &cp)
X86: Fold the MiscRegFile all the way into the ISA object.
2009-07-10 05:29:02 +02:00
{
UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
x86: minor checkpointing bug fixes
2010-08-17 14:20:39 +02:00
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
X86: Move address based decode caching in front of the predecoder. The predecoder in x86 does a lot of work, most of which can be skipped if the decoder cache is put in front of it. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-05 02:00:44 +01:00
regVal[MISCREG_RFLAGS],
NULL);
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-07-09 08:02:20 +02:00
}
x86: Changes to decoder, corrects 9376 The changes made by the changeset 9376 were not quite correct. The patch made changes to the code which resulted in decoder not getting initialized correctly when the state was restored from a checkpoint. This patch adds a startup function to each ISA object. For x86, this function sets the required state in the decoder. For other ISAs, the function is empty right now.
2013-01-13 05:09:48 +01:00
void
ISA::startup(ThreadContext *tc)
{
tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
}
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-07-09 08:02:20 +02:00
}
arch: Make the ISA class inherit from SimObject The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2013-01-07 19:05:35 +01:00
X86ISA::ISA *
X86ISAParams::create()
{
return new X86ISA::ISA(this);
}
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