2016-05-31 17:55:47 +02:00
---------- Begin Simulation Statistics ----------
2016-08-12 15:12:59 +02:00
sim_seconds 0.058750 # Number of seconds simulated
sim_ticks 58750410500 # Number of ticks simulated
final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 179920 # Simulator instruction rate (inst/s)
host_op_rate 230092 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 149057017 # Simulator tick rate (ticks/s)
host_mem_usage 281832 # Number of bytes of host memory used
host_seconds 394.15 # Real time elapsed on the host
2016-05-31 17:55:47 +02:00
sim_insts 70915150 # Number of instructions simulated
sim_ops 90690106 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory
system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory
system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory
system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory
system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 128515 # Number of read requests accepted
system.physmem.writeReqs 86552 # Number of write requests accepted
system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
2016-05-31 17:55:47 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::0 8086 # Per bank write bursts
system.physmem.perBankRdBursts::1 8335 # Per bank write bursts
system.physmem.perBankRdBursts::2 8257 # Per bank write bursts
system.physmem.perBankRdBursts::3 8155 # Per bank write bursts
system.physmem.perBankRdBursts::4 8301 # Per bank write bursts
system.physmem.perBankRdBursts::5 8413 # Per bank write bursts
system.physmem.perBankRdBursts::6 8070 # Per bank write bursts
system.physmem.perBankRdBursts::7 7917 # Per bank write bursts
system.physmem.perBankRdBursts::8 8053 # Per bank write bursts
system.physmem.perBankRdBursts::9 7612 # Per bank write bursts
system.physmem.perBankRdBursts::10 7771 # Per bank write bursts
system.physmem.perBankRdBursts::11 7825 # Per bank write bursts
system.physmem.perBankRdBursts::12 7888 # Per bank write bursts
system.physmem.perBankRdBursts::13 7870 # Per bank write bursts
system.physmem.perBankRdBursts::14 7981 # Per bank write bursts
system.physmem.perBankRdBursts::15 7974 # Per bank write bursts
system.physmem.perBankWrBursts::0 5399 # Per bank write bursts
system.physmem.perBankWrBursts::1 5549 # Per bank write bursts
system.physmem.perBankWrBursts::2 5476 # Per bank write bursts
system.physmem.perBankWrBursts::3 5348 # Per bank write bursts
system.physmem.perBankWrBursts::4 5387 # Per bank write bursts
system.physmem.perBankWrBursts::5 5588 # Per bank write bursts
system.physmem.perBankWrBursts::6 5325 # Per bank write bursts
system.physmem.perBankWrBursts::7 5260 # Per bank write bursts
system.physmem.perBankWrBursts::8 5187 # Per bank write bursts
system.physmem.perBankWrBursts::9 5136 # Per bank write bursts
system.physmem.perBankWrBursts::10 5306 # Per bank write bursts
system.physmem.perBankWrBursts::11 5279 # Per bank write bursts
system.physmem.perBankWrBursts::12 5541 # Per bank write bursts
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system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankWrBursts::14 5706 # Per bank write bursts
system.physmem.perBankWrBursts::15 5441 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-08-12 15:12:59 +02:00
system.physmem.totGap 58750379000 # Total gap between requests
2016-05-31 17:55:47 +02:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 128515 # Read request sizes (log2)
2016-05-31 17:55:47 +02:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.writePktSize::6 86552 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
2016-07-21 18:19:18 +02:00
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-08-12 15:12:59 +02:00
system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads
system.physmem.totQLat 1552277750 # Total ticks spent queuing
system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.83 # Data bus utilization in percentage
2016-07-21 18:19:18 +02:00
system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads
2016-08-12 15:12:59 +02:00
system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes
2016-05-31 17:55:47 +02:00
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
2016-08-12 15:12:59 +02:00
system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing
system.physmem.readRowHits 112029 # Number of row buffer hits during reads
system.physmem.writeRowHits 70027 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes
system.physmem.avgGap 273172.45 # Average gap between requests
system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ)
system.physmem_0.averagePower 705.717335 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states
2016-05-31 17:55:47 +02:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states
2016-05-31 17:55:47 +02:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ)
system.physmem_1.averagePower 704.382975 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states
system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states
2016-05-31 17:55:47 +02:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states
2016-05-31 17:55:47 +02:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 14827613 # Number of BP lookups
system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits
2016-05-31 17:55:47 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-08-12 15:12:59 +02:00
system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target.
2016-05-31 17:55:47 +02:00
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
2016-08-12 15:12:59 +02:00
system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches.
2016-05-31 17:55:47 +02:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 117500821 # number of cpu cycles simulated
2016-05-31 17:55:47 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915150 # Number of instructions committed
system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
2016-08-12 15:12:59 +02:00
system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit
2016-05-31 17:55:47 +02:00
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
2016-08-12 15:12:59 +02:00
system.cpu.cpi 1.656921 # CPI: cycles per instruction
system.cpu.ipc 0.603529 # IPC: instructions per cycle
2016-05-31 17:55:47 +02:00
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 90690106 # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked
system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 156451 # number of replacements
system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits
2016-05-31 17:55:47 +02:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits
system.cpu.dcache.overall_hits::total 42605646 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses
system.cpu.dcache.overall_misses::total 299891 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency
2016-05-31 17:55:47 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks
system.cpu.dcache.writebacks::total 128145 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles
2016-05-31 17:55:47 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 43545 # number of replacements
system.cpu.icache.tags.tagsinuse 1854.190293 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25047618 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 549.446509 # Average number of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1854.190293 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.905366 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.905366 # Average percentage of cache occupancy
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses
system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits
system.cpu.icache.overall_hits::total 25047618 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses
system.cpu.icache.overall_misses::total 45588 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 918433000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 918433000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 918433000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 918433000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 918433000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 918433000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20146.376239 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20146.376239 # average overall miss latency
2016-05-31 17:55:47 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.icache.writebacks::writebacks 43545 # number of writebacks
system.cpu.icache.writebacks::total 43545 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 872846000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 872846000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 872846000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 872846000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 872846000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 872846000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 97176 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 10596662000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 480.299456 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1381.968758 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29466.192474 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.014658 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042174 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.899237 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.956069 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1189 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13615 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17003 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41100 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 41100 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 41100 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 77546 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 41100 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits
system.cpu.l2cache.overall_hits::total 77546 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4488 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 4488 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 4488 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 128589 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 4488 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses
system.cpu.l2cache.overall_misses::total 128589 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8191072500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8191072500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 369038000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 369038000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1957896000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1957896000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 369038000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10148968500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10518006500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 369038000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10148968500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10518006500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses)
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098447 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098447 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098447 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.623810 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098447 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.623810 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80055.831387 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80055.831387 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82227.718360 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82227.718360 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89877.708410 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89877.708410 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks
system.cpu.l2cache.writebacks::total 86552 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 97176 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks)
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks)
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 26198 # Transaction distribution
system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution
system.membus.trans_dist::CleanEvict 7237 # Transaction distribution
system.membus.trans_dist::ReadExReq 102317 # Transaction distribution
system.membus.trans_dist::ReadExResp 102317 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.membus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::samples 128515 # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram
2016-05-31 17:55:47 +02:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::total 128515 # Request fanout histogram
system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks)
2016-05-31 17:55:47 +02:00
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks)
2016-05-31 17:55:47 +02:00
system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
